1.3.2. Preventing damage

The Logic Tile is intended for use within a laboratory or engineering development environment. It is supplied without an enclosure which leaves the board sensitive to electrostatic discharges and allows electromagnetic emissions.

Caution

To avoid damage to the board, observe the following precautions.

  • Never subject the board to high electrostatic potentials. Observe ElectroStatic Discharge (ESD) precautions when handling any board.

  • Always wear a grounding strap when handling the board.

  • Only hold the board by the edges.

  • Avoid touching the component pins or any other metallic element.

  • Ensure that the voltage on the pins of the FPGA and interface circuitry on all connected Logic Tiles is at the correct level. If you are using a PB926EJ-S, or an EB baseboard, some of the Logic Tile FPGA signals are connected directly to the baseboard.

  • FPGA pins connected to an external signal source must not be configured as outputs.

  • Do not use the board near a transmitter of electromagnetic emissions.

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