2.2.1. Switches

There are two DIP switch banks fitted to the Logic Tile:

Note

The DIP switches used are labelled from one not zero, so that is the numbering convention used in this guide.

S1[8:1]

These switches are general purpose switches that are user-defined.

S2[2:1]

These switches select the image to load into the FPGA at power-on.

The Flash is preloaded with two configuration images. If S2[1] is ON, the image selected is determined by the global signal FPGA_IMAGE from the HDRZ header. If S2[1] is OFF, the image selected is determined locally by S2[2]. For a full description of FPGA configuration image selection, see Configuring the FPGA from Flash.

S3

This push-button is a general-purpose switch.

The signal is buffered and connected to the PLD. If the push-button is depressed, then the signal to the FPGA is LOW.

To reduce the number of FPGA I/O pins required, the PLD provides S1[8:1] and S3 switch status to the FPGA using the serial link (SDI) between the two devices. Signal routing depends on the operating mode of the LT-XC4VLX100+. Table 2.1 lists the operating modes and the signal routing in each mode.

Table 2.1. Switch signal routing

ModeCFGENLOCAL_DONEFunction
ConfigurationHIGHDon’t careFlash programming. Switch status is not available in this mode.
Debug: Configure from Flash LOWLOWFPGA configuration. On power up, FPGA image selection switches, S2[2:1] determine the configuration data transferred by the PLD to the FPGA. See Configuring the FPGA from Flash for details.
Debug: Normal operationLOWHIGHNormal operation. User switches, S1[8:1] status is transferred serially by the PLD to the FPGA. Push-button, S3 status is transferred by the PLD to the FPGA. See PLD for interconnect details.
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