2.2.2. LEDs

There are three individual status LEDs and a single bank of eight User LEDs:

FPGA IMAGE

This LED indicates the image that is loaded into the FPGA. It is lit if the image from the top half of the Flash memory is selected and off if the image from the bottom half of the Flash memory is selected.

FPGA OK

This LED indicates that FPGA configuration has completed.

OVER TEMP

This LED indicates that the FPGA is operating above a safe temperature. The temperature monitor lights the LED once the FPGA temperature exceeds 80°C.

Caution

If the temperature monitor lights, turn off the supply immediately. Prolonged over heating may damage the board or the Virtex-4 device itself. Check for all possible causes such as excessive I/O loading, I/O contention, or the board being over-clocked. Whenever possible, remove the cause of overheating before re-powering the board.

USER[7:0]

These LEDs are general purpose indicators and are user-defined.

The User[7:0] LED control signals from the FPGA are routed through the PLD. To reduce the number of FPGA I/O pins required, the USER[7:4] signals are routed using the serial link (SDO) between the two devices. The signal routing depends on the operating mode of the LT-XC4VLX100+. Table 2.2 lists the operating modes and the signal routing in each mode.

Table 2.2. User signal routing

ModeCFGENLOCAL_DONEFunction
ConfigurationHIGHDon’t careFlash programming. User LED control is not available in this mode. S3 not pressed: USER[7:0] LEDs display the current Flash memory address being programmed. S3 pressed: User[7:0] LEDs display the PLD build version.
Debug: Configure from FlashLOWLOWFPGA configuration. User LED control is not available in this mode.
Debug: Normal operationLOWHIGHNormal operation. User[3:0] LED control is transferred directly by the FPGA to the PLD. User[7:4] LED control is transferred serially by the FPGA to the PLD. See PLD for interconnect details.

The PLD sources current to the LEDs through 330Ω resistors, a logic high on the PLD output lights the LED.

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