4.2.2. Place and route

Place and route for this Logic Tile type is performed using Xilinx-specific software. This produces a .bit file that is used to program the FPGA. The .bit file is targeted at a particular device, taking into account the device size, package type, and speed grade.

The full part numbers for the Virtex-4 FPGAs fitted on the LT-XC4VLX100+ are:


When using the Xilinx tools to generate the programming file (.bit file), always specify CCLK as the start up clock for your FPGA designs that are to be stored in Flash.

In Configuration mode, the JTAG start-up clock is used to directly configure the FPGA.

Signal names from the top-level HDL are mapped onto actual device pins by a user constraints file .ucf. You can also specify the timing requirements within this file.


The pin constraints file (.ucf) for the complete Logic Tile FPGA pin allocation is supplied on the CD. This is intended as a starting point for any design, and must be edited before use in the place and route process.

Current Xilinx tools (ISE 8.102) support bit-file compression. This reduces the size of the bit file and reduces the Progcards utility programming times.

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