These intrinsics add vectors. Each lane in the result is the consequence of performing the addition on the corresponding lanes in each operand vector. The operations performed are as follows:

Vr, Va, Vb have equal lane sizes.

```int8x8_t    vadd_s8(int8x8_t a, int8x8_t b);         // VADD.I8 d0,d0,d0
```

Va, Vb have equal lane sizes, result is a 128 bit vector of lanes that are twice the width.

```int16x8_t  vaddl_s8(int8x8_t a, int8x8_t b);      // VADDL.S8 q0,d0,d0
```

```int16x8_t  vaddw_s8(int16x8_t a, int8x8_t b);     // VADDW.S8 q0,q0,d0
```

```int8x8_t   vhadd_s8(int8x8_t a, int8x8_t b);       // VHADD.S8 d0,d0,d0
```

```int8x8_t   vrhadd_s8(int8x8_t a, int8x8_t b);       // VRHADD.S8 d0,d0,d0
```

```int8x8_t   vqadd_s8(int8x8_t a, int8x8_t b);       // VQADD.S8 d0,d0,d0
```

#### Vector add high half -> Vr[i]:=Va[i]+Vb[i]

```int8x8_t   vaddhn_s16(int16x8_t a, int16x8_t b);   // VADDHN.I16 d0,q0,q0
```

#### Vector rounding add high half

```int8x8_t   vraddhn_s16(int16x8_t a, int16x8_t b);   // VRADDHN.I16 d0,q0,q0