RealView Platform Baseboard for ARM11 MPCore User Guide: 3.14.3. Distributed Interrupt Controller routing

A total of 32 interrupt lines, INT[31:0] are provided by the Distributed Interrupt Controller in the ARM11 MPCore:

Interrupt lines INT[31:16] are used internally by the ARM11 MPCore test chip. See Interrupt Routing for details of their use.
Interrupt lines INT[15:0] are available for external use and routing is controlled by the PB11MPCore.

Three routing options are provided:

See PLD control register 1, SYS_PLD_CTRL1 for details of the INTMODE[2:0] field that controls the routing mode.

Table 3.3 lists Legacy Mode interrupt routing for ARM11 MPCore INT[15:0] (INTMODE = b000).

Table 3.3. Legacy Mode: INT[15:0]

Table 3.4 lists Legacy Mode interrupt routing for ARM11 MPCore nIRQ and nFIQ (INTMODE = b0000).

Table 3.4. Legacy Mode: nIRQ and nFIQ

Table 3.5 lists new mode with DCC interrupt routing for ARM11 MPCore INT[15:0] (INTMODE = b001).

Table 3.5. New Mode with DCC: INT[15:0]

Table 3.6 lists New Mode with DCC interrupt routing for ARM11 MPCore nIRQ and nFIQ (INTMODE = b001).

Table 3.6. New Mode with DCC: nIRQ and nFIQ

ARM11 MPCore nIRQ and nFIQ	ARM11 MPCore CPU	Source
nIRQ[3:0]	CPU#[3:0]	`b1111`
nFIQ[3:0]	CPU#[3:0]	`b1111`

Table 3.7 lists new mode without DCC interrupt routing for ARM11 MPCore INT[15:0] (INTMODE = b010).

Table 3.7. New mode without DCC: INT[15:0]

Table 3.8 lists New Mode without DCC interrupt routing for ARM11 MPCore nIRQ and nFIQ (INTMODE = b010).

Table 3.8. New Mode without DCC: nIRQ and nFIQ

ARM11 MPCore nIRQ and nFIQ	ARM11 MPCore CPU	Source
nIRQ[3:0]	CPU#[3:0]	`b1111`
nFIQ[3:0]	CPU#[3:0]	`b1111`

Copyright © 2007-2011 ARM Limited. All rights reserved.	ARM DUI 0351E
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