RealView Platform Baseboard for ARM11 MPCore User Guide: 3.13. Resets

3.13. Resets

The resets domains for the PB11MPCore are shown in Figure 3.15.

Figure 3.15. Reset routing

The Reset Controller state diagram is shown in Figure 3.16

Figure 3.16. Reset Controller state diagram

The reset timing is shown in Figure 3.17.

Figure 3.17. Reset timing

Note

If a peripheral implemented on a Logic Tile fitted to the tile site needs to generate a system level reset it can pulse the nSRST signal low. This will cause the nSYSRST signal to pulse low resetting the system. This is a system level reset, it will not generate a power on reset.

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