RealView® Platform Baseboard for ARM11 MPCore User Guide

HBI-0159 HBI-0175 HBI-0176

Table of Contents

About this book
Intended audience
Using this book
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the PB11MPCore
1.1.1. ARM11 MPCore test chip
1.1.2. Northbridge
1.1.3. Southbridge
1.1.4. PB11MPcore expansion
1.2. Precautions
1.2.1. Ensuring safety
1.2.2. Preventing damage
2. Getting Started
2.1. Setting up the baseboard
2.2. Boot Monitor configuration
2.3. JTAG debugger and USB config support
2.3.1. JTAG debugger
2.3.2. USB config port
2.4. Baseboard configuration switches
2.4.1. Boot memory configuration
2.4.2. Fast mode
2.4.3. Flash recovery
2.4.4. Level 2 Cache fix enable
2.4.5. MPMASTNUM selection
3. Hardware Description
3.1. Baseboard architecture
3.1.1. Enclosure front panel
3.1.2. Enclosure rear panel
3.1.3. System architecture
3.1.4. Northbridge
3.1.5. Southbridge
3.1.6. PCI bus connectors
3.1.7. Displays
3.1.8. Logic Tile expansion
3.1.9. Clock generation
3.1.10. Debug and test interfaces
3.2. Tile interconnections
3.2.1. AXI bus multiplexing
3.3. ARM11 MPCore test chip
3.3.1. ARM11 MPCore test chip overview
3.4. Northbridge
3.4.1. ARM11 MPCore test chip interface
3.4.2. CLCD controller
3.4.3. Memory controllers
3.4.4. Multiplexed AHB-Lite interface
3.4.5. Multiplexed AXI interfaces
3.4.6. PCI interface
3.5. Southbridge
3.5.1. FPGA configuration
3.5.2. Reset controller
3.5.3. CompactFlash
3.5.4. APB peripherals
3.6. Ethernet interface
3.7. USB Interface
3.8. USB config interface
3.9. DVI Interface
3.10. PCI interface
3.11. Power supply control
3.11.1. Setting the ARM11 MPCore test chip voltages
3.11.2. Reading the ARM11 MPCore test chip voltages
3.11.3. Reading the ARM11 MPCore test chip currents
3.12. Clock architecture
3.12.1. PB11MPCore clocks
3.12.2. PCI and PCI Express clocks
3.12.3. ARM11 MPCore test chip clocks
3.13. Resets
3.14. Interrupts
3.14.1. Generic Interrupt Controller, GIC
3.14.2. ARM11 MPCore Distributed Interrupt Controller
3.14.3. Distributed Interrupt Controller routing
3.15. Test, configuration, and debug interfaces
3.15.1. Debug and Config port support
3.15.2. Integrated logic analyzer (ILA)
4. Programmer’s Reference
4.1. Memory map
4.2. Configuration and initialization
4.2.1. Remapping of boot memory
4.2.2. Memory characteristics
4.3. Status and system control registers
4.3.1. ID Register, SYS_ID
4.3.2. User Switch Register, SYS_USERSW
4.3.3. LED Register, SYS_LED
4.3.4. Oscillator Registers, SYS_OSCx
4.3.5. Lock Register, SYS_LOCK
4.3.6. 100Hz Counter, SYS_100HZ
4.3.7. Flag Registers, SYS_FLAGSx and SYS_NVFLAGSx
4.3.8. Reset Control Register, SYS_RESETCTL
4.3.9. MCI Register, SYS_MCI
4.3.10. Flash Control Register, SYS_FLASH
4.3.11. CLCD Control Register, SYS_CLCD
4.3.12. Configuration select switch, SYS_CFGSW
4.3.13. 24MHz Counter, SYS_24MHZ
4.3.14. Miscellaneous flags, SYS_MISC
4.3.15. DMA peripheral map register, SYS_DMAPSR
4.3.16. PCI Express status register, SYS_PEX_STAT
4.3.17. PCI status register, SYS_PCI_STAT
4.3.18. PLD control register 1, SYS_PLD_CTRL1
4.3.19. PLD control register 2, SYS_PLD_CTRL2
4.3.20. PLD initialization register, SYS_PLD_INIT
4.3.21. Processor ID register 0, SYS_PROCID0
4.3.22. Processor ID register 1, SYS_PROCID1
4.3.23. Oscillator reset registers, SYS_OSCRESETx
4.3.24. Voltage control registers, SYS_VOLTAGE_CTLx
4.3.25. Oscillator test registers, SYS_TEST_OSCx
4.4. System Controller (SYSCTRL)
4.4.1. PrimeCell modifications
4.5. Advanced Audio CODEC Interface, AACI
4.5.1. PrimeCell Modifications
4.6. Color LCD Controller, CLCDC
4.6.1. Display resolutions and display memory organization
4.7. Single Master Direct Memory Access Controller, SMDMAC
4.7.1. DMAC flow control
4.7.2. DMA channel allocation
4.8. Dynamic Memory Controller, DMC
4.8.1. Register values
4.9. Ethernet
4.10. General Purpose Input/Output, GPIO
4.10.1. Onboard I/O control
4.11. Generic Interrupt Controller, GIC
4.11.1. Interrupt signals
4.11.2. Handling interrupts
4.12. Keyboard and Mouse Interface, KMI
4.13. MultiMedia Card Interface, MCI
4.14. AXI to PCI bridge
4.15. Real Time Clock, RTC
4.16. Two-wire serial bus interface, SBCon
4.17. Smart Card Interface, SCI
4.18. Synchronous Serial Port, SSP
4.19. Static Memory Controller, SMC
4.20. Timers
4.21. UART
4.21.1. Variations from the 16C550 UART
4.22. USB interface
4.23. Watchdog
4.24. CompactFlash interface
4.24.1. CompactFlash Control Register, CF_CTRL
5. Processor Sub-System
5.1. ARM11 MPCore test chip overview
5.2. Clocks
5.2.1. Clocking overview
5.2.2. PLL
5.2.3. PLL bypass module
5.2.4. Clock signals overview
5.3. Resets and interrupts
5.3.1. Resets
5.3.2. Interrupts
5.4. Power supply control
5.5. Memory configuration
5.5.1. ARM11 MPCore
5.5.2. L220 cache controller
5.6. L220 bypass and peripheral decode
5.6.1. L220 bypass module
5.6.2. Peripheral decoder
5.7. Debug and configuration using JTAG
5.7.1. TAP controller
5.7.2. Debug
5.7.3. Configuration using JTAG
5.7.4. TAP ID registers
A. Signal Descriptions
A.1. Compact Flash interface
A.2. Audio CODEC interface
A.3. MMC and SD card interface
A.4. Keyboard and mouse interface
A.5. GPIO interface
A.6. UART interface
A.7. Synchronous Serial Port interface
A.8. Smart Card interface
A.9. Ethernet interface
A.10. USB interface
A.11. DVI display interface
A.12. RealView Logic Tile header connectors
A.12.1. HDRX signals
A.12.2. HDRY signals
A.12.3. HDRZ
A.13. Test and debug connections
A.13.1. JTAG
A.13.2. USB config port
A.13.3. Integrated Logic Analyzer (ILA)
B. Specifications
B.1. Electrical Specification
B.1.1. Bus interface characteristics
B.2. Timing specifications
B.2.1. Clock frequency restrictions
B.2.2. AXI bus timings
C. Memory Expansion Boards
C.1. About memory expansion
C.1.1. Operation without expansion memory
C.1.2. Memory board configuration
C.2. Fitting a memory board
C.3. Connector pinout
C.3.1. Expansion connector
D. RealView Logic Tile expansion
D.1. About the RealView Logic Tile
D.2. Header connectors
D.2.1. Variable I/O levels
D.2.2. RealView Logic Tile clocks
D.2.3. JTAG
D.2.4. AXI buses used by the Northbridge and RealView Logic Tiles
D.2.5. Reset
E. Boot Monitor and platform library
E.1. About the Boot Monitor
E.2. About the platform library
E.3. Using the baseboard Boot Monitor and platform library
E.3.1. Boot Monitor configuration switches
E.3.2. Running the Boot Monitor
E.3.3. Loading Boot Monitor into NOR flash
E.3.4. Redirecting character output to hardware devices
E.3.5. Using a boot script to run an image automatically
E.3.6. Rebuilding the Boot Monitor or platform library
E.3.7. Building an application with the platform library
E.3.8. Building an application that uses semihosting
E.3.9. Loading and running an application from NOR flash
E.3.10. Running an image from MMC or SD card or CompactFlash
E.3.11. Using the Network Flash Utility
F. Boot Monitor Commands
F.1. About Boot Monitor commands
F.2. Boot Monitor command set
G. Loading FPGA Images
G.1. General procedure
G.2. Board files
G.2.1. Naming conventions for board files
G.2.2. Naming conventions for image files
G.3. The progcards utilities
G.4. Upgrading your hardware
G.4.1. Procedure for progcards_rvi.exe
G.4.2. Procedure for progcards_usb.exe
G.4.3. Troubleshooting

List of Figures

1. Key to timing diagram conventions
1.1. PB11MPCore system architecture
3.1. Baseboard layout
3.2. Front panel layout
3.3. Rear panel layout
3.4. PB11MPCore top level block diagram
3.5. Main tile and system bus routing
3.6. Top-level view of ARM11 MPCore test chip
3.7. Northbridge block diagram
3.8. Southbridge block diagram
3.9. PCI-PCI Express interface
3.10. Voltage control and voltage and current monitoring
3.11. Clock architecture
3.12. Northbridge clock domains
3.13. PCI and PCI Express clock routing
3.14. ARM11 MPCore test chip clocks
3.15. Reset routing
3.16. Reset Controller state diagram
3.17. Reset timing
3.18. External and internal interrupt sources
4.1. System memory map for standard peripherals
4.2. SYS_ID register
4.3. SYS_USERSW register
4.4. SYS_LED register
4.5. SYS_OSCx register
4.6. SYS_LOCK register
4.7. 100Hz Counter, SYS_100HZ register
4.8. SYS_RESETCTL register
4.9. SYS_MCI register
4.10. SYS_FLASH register
4.11. SYS_CLCD register
4.12. SYS_CFGSW register
4.13. SYS_24MHZ register
4.14. SYS_MISC register
4.15. SYS_DMAPSR register
4.16. SYS_PEX_STAT register
4.17. SYS_PCI_STAT register
4.18. SYS_PLD_CTRL1 register
4.19. SYS_PLD_CTRL2 register
4.20. SYS_PLD_INIT register
4.21. SYS_PROCID0 register
4.22. SYS_PROCID1 register
4.23. SYS_OSCRESETx register
4.24. AACI ID register
4.25. CF_CTRL Register
5.1. Top-level view of ARM11 MPCore test chip
5.2. Clock domain overview
5.3. PLL block diagram
5.4. Test chip interrupt control register
5.5. Test chip power status register
5.6. L220 data RAM organization
5.7. L220 bypass mechanism
5.8. MPCore and L220 port configurations
5.9. TAP signal connections between the four ARM11 MPCore CPUs
5.10. TAP ID register
A.1. Compact Flash connector pin numbering
A.2. Audio connectors
A.3. MMC/SD card socket pin numbering
A.4. MMC card
A.5. KMI connector
A.6. GPIO connector
A.7. Serial connector
A.8. SSP expansion interface
A.9. Smartcard contacts assignment
A.10. SCI expansion
A.11. Ethernet connector
A.12. USB connectors
A.13. DVI connector
A.14. HDRX, HDRY, and HDRZ pin numbering
A.15. JTAG connector
A.16. USB debug connector
A.17. Integrated Logic Analyzer (ILA) connector
B.1. Tile site multiplexed AXI timing
C.1. Static memory board block diagram
C.2. Samtec 120-way connector
D.1. Signals on the RealView Logic Tile expansion connectors
D.2. HDRX, HDRY, and HDRZ (upper) pin numbering

List of Tables

2.1. Boot Monitor startup behavior
2.2. STDIO redirection
2.3. Selecting the boot device
2.4. Selecting fast mode
2.5. ARM11 MPCore reset behavior
2.6. Enable Level 2 Cache fix
2.7. Number of ARM11 MPCore AXI ports
3.1. FPGA image selection
3.2. Serial interface device addresses
3.3. Legacy Mode: INT[15:0]
3.4. Legacy Mode: nIRQ and nFIQ
3.5. New Mode with DCC: INT[15:0]
3.6. New Mode with DCC: nIRQ and nFIQ
3.7. New mode without DCC: INT[15:0]
3.8. New Mode without DCC: nIRQ and nFIQ
4.1. System memory map
4.2. Memory map for standard peripherals
4.3. Boot memory
4.4. Memory chip selects and address range
4.5. Register map for status and system control registers
4.6. SYS_ID register bit assignments
4.7. SYS_OSCx register bit assignments
4.8. SYS_LOCK register bit assignments
4.9. Flag registers
4.10. SYS_RESETCTL register bit assignments
4.11. SYS_MCI register bit assignment
4.12. SYS_FLASH register bit assignments
4.13. SYS_CLCD register bit register assignments
4.14. SYS_MISC register bit assignment
4.15. SYS_DMAPSR register bit assignments
4.16. SYS_DMAPSR register bit coding
4.17. SYS_PEX_STAT register bit assignments
4.18. SYS_PCI_STAT register bit assignments
4.19. SYS_PLD_CTRL1 register bit assignments
4.20. SYS_PLD_CTRL2 register bit assignments
4.21. SYS_PLD_INIT register bit assignments
4.22. SYS_PROCID0 register bit assignments
4.23. SYS_PROCID1 register bit assignments
4.24. SYS_VOLTAGE_CTLx registers
4.25. SYS_TEST_OSCx registers
4.26. SYSCTRL implementation
4.27. SYS_CTRL0 register
4.28. SYS_CTRL1 register
4.29. AACI implementation
4.30. Modified AACI PeriphID3 register
4.31. CLCDC implementation
4.32. Values for different display resolutions
4.33. SMDMAC implementation
4.34. DMC implementation
4.35. Ethernet implementation
4.36. GPIO implementation
4.37. GPIO2 and MCI status signals
4.38. Generic Interrupt Controller implementation
4.39. Interrupt signals to controllers
4.40. KMI implementation
4.41. MCI implementation
4.42. AXI to PCI bridge implementation
4.43. PCI bus memory map
4.44. RTC implementation
4.45. Serial bus implementation
4.46. Serial interface device addresses
4.47. SBCon 0 serial bus register
4.48. SBCon 1 serial bus register
4.49. Serial bus device addresses
4.50. SCI implementation
4.51. SSP implementation
4.52. SMC implementation
4.53. Timer implementation
4.54. UART implementation
4.55. USB implementation
4.56. USB controller base address
4.57. Watchdog implementation
4.58. CompactFlash implementation
4.59. CF_CTRL register bit assignments
5.1. PLL frequency limits for different divisors
5.2. Clock signals
5.3. Reset handling
5.4. Reset deassertion with respective clock
5.5. Test chip interrupt control register
5.6. Internal interrupt lines
5.7. Test chip power status register
5.8. Most Useful settings of the L2BYPASS and MPMASTNUM configuration bits
5.9. Peripheral decoder mapping
5.10. Test chip TAP instructions
5.11. ARM11 MPCore TAP ID register
5.12. Test chip TAP ID register
A.1. Compact Flash connector pinout
A.2. Multimedia Card interface signals
A.3. Mouse and keyboard port signal descriptions
A.4. Serial plug signal assignment
A.5. SSP signal assignment
A.6. Smartcard connector signal assignment
A.7. Signals on SCI expansion connector
A.8. Ethernet signals
A.9. DVI connector signals
A.10. HDRX signals
A.11. HDRY signals
A.12. HDRZ signals
B.1. Baseboard electrical characteristics
B.2. AC Specifications
C.1. Static memory connector signals
E.1. STDIO redirection
E.2. platform library options
E.3. NFU commands
E.4. NFU MANAGE commands
F.1. Standard Boot Monitor command set
F.2. MMC, SD, and CompactFlash card sub-menu commands
F.3. Boot Monitor Configure commands
F.4. Boot Monitor Debug commands
F.5. Boot Monitor NOR flash commands

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

The PB11MPCore generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AOctober 2007New document
Revision BMay 2008Fixes for Errata
Revision CMarch 2009Fixes for Errata
Revision DJuly 2010Document update
Revision EApril 2011Document update
Copyright © 2007-2011 ARM Limited. All rights reserved.ARM DUI 0351E