ARM® RealView® ESL API v2.0 Developer’s Guide C.1. Introduction to AXI

C.1. Introduction to AXI

AXI is a point to point connection between a single master and a single slave interface.

Note

Multiple masters can, however, communicate with multiple slaves by using a matrix component that manages arbitration, multiplexing, and address decoding.

The AXI protocol is implemented by five independent channels:

Write address channel (AW): This channel communicates the address from the master to the slave for write requests. This channel also communicates information about the write access (for example, write burst count and word size).
Write data channel (W): This channel communicates the write data from the master to the slave.
Write response channel (B): This channel communicates the status from the slave to a write request from the master and indicates whether the write attempt was successful. The AXI slave drives the status (typically OKAY) onto the response channel.
Read address channel (AW): This channel communicates the address from the master to the slave for read requests. The channel also communicates information about the read access (for example, read burst count and word size).
Read data channel (R): This channel communicates the data and status from the slave to the master for read requests. The AXI slave drives the data and status onto the data channel.

A block diagram of two components that communicate over an AXI bus is shown in Figure C.1:

Figure C.1. Block diagram of master and slave components connected over an AXI bus

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