ARM® RealView® ESL API v2.0 Developer’s Guide C.2. Introduction to the CASI TLM for AXI

C.2. Introduction to the CASI TLM for AXI

This section describes how the CASI TLM for AXI uses data structures and access functions to provide a simulation equivalent to the AXI hardware bus.

The TLM API does not contain five distinct pairs of master/slave ports that were shown in Figure C.1 for the hardware implementation. The communication between the master and slave ports is done by passing a transaction info structure between the driveTransaction() and notifyEvent() functions. The signals that are managed by the hardware channels in a physical system are managed by multiple calls to driveTransaction() and notifyEvent() in the TLM API.

Figure C.3 shows a simplified block diagram of a system consisting of:

a component named AXI_Master_casi that contains an AXI master port.
a component named AXI_Slave_casi that contains an AXI slave port.

Figure C.3. Simplified AXI TLM block diagram

The classes and structures used to implement the AXI TLM are shown in Figure C.4:

Figure C.4. AXI classes

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