Example 2.2. CASIModule class

class CASIModule : public CASIClockSlaveIF, public CASIModuleIF,
        public sc_module
{
public:
    /* Constructor / Destructor */
    CASIModule(const sc_module_name & name, CASIModuleIF *_parent);
    CASIModule(CASIModuleIF *_parent, const sc_module_name & name);
    CASIModule();
    virtual ~CASIModule();
    
    // Functions called each cycle during the cycle-accurate simulation.
    // Ensure that the communicate and update functions of clocked
    // components are implemented in the component
    virtual void communicate (){ 
         message(CASI_MSG_ERROR, "Default communicate called.");
    }
    virtual void update (){
        message(CASI_MSG_ERROR, "Default update called.");
    }

    /* Functions for the different stages of simulation */
    virtual void configure();
    virtual void init();
    virtual void interconnect();
    virtual void reset(CASIResetLevel level, 
        const CASIFileMapIF *filelist =NULL);
    virtual void terminate();

    /* Functions for identification */
    virtual std::string getName() = 0;
    virtual CASIInterfaceType getType();
    virtual std::string getInstanceName();
    virtual std::string getInstanceID();

    // Functions for model parameters
    virtual std::string getProperty (CASIPropertyType property);
    virtual void setParameter(const std::string & key, 
        const std::string & value);
    virtual std::string getParameter(const std::string & key);

    // Interface with CADI/CAPI
    virtual CADI * getCADI();
    virtual CAPI * getCAPI();

    virtual int getNumCAMMIs (); 
    virtual CAMMI * getCAMMI (int index = 0);
 
    // Helper functions
    virtual void casi_clocked(void);
    virtual void casi_clocked(CASIPhase _phases);

    // Retrieves the parameter list.
    const CASIParameterMapIF* getParameterList();
    // Checks to see if a parameter is valid.
    virtual bool testParameter(const std::string& key, 
        const std::string& value, std::string& error_message) 
        { return true; }
    // Registers a port.
    void registerPort(CASIPortIF* port, const std::string& name);
    void registerPortArray(CASIPortIF** port, const std::string& name);
    void exportPort(CASIPortIF *c, const std::string& portName,
        const std::string& extPortName);
    CASIPortIF* createPort(CASIInterfaceType type, 
        const std::string& name, int ID = 0);
    CASIPortIF* findPort(const std::string& name);
    const CASIPortMapIF* getPortList();

    // Creates a subcomponent based on dynamic component creation.
    // Currently dynamic component creation is not fully supported.
    CASIModuleIF * createSubcomponent( const std::string& type,
        const std::string& name);
    // Creates a subcomponent based on dynamic component creation.
    // Currently dynamic component creation is not fully supported.
    // Unix/ELF specific function.
    CASIModuleIF * createSubcomponent( bool bDlopenGlobal,
        const std::string& type, const std::string& name);
    // Adds a child subcomponent.
    void addSubcomponent(CASIModuleIF *c);
    CASIModuleIF *getSubcomponent(const std::string &name);
    const std::vector<CASIModuleIF*>& getSubcomponentList();

    // Sets a parameter for a subcomponent.
    void setSubcomponentParameter(const std::string& name,
        const std::string& key, const std::string& value);
    // Connects subcomponent ports.
    void connect_ports(const std::string& comp1, const std::string& port1,
        const std::string& comp2, const std::string& port2);
    void setClockMaster(CASIClockMasterIF *clockFromParent);
    CASIClockMasterIF *getClockMaster();
    virtual CASIModuleIF * getParent() { return parent; }

    // Prints a message.
    virtual void message( const std::string& msg, 
        CASIMessageType type = CASI_MSG_INFO );
    // Prints a message, vararg variant.
    virtual void message( CASIMessageType type, const char *fmt, ... );
    virtual CASIComponentLayout* getComponentLayout() { return NULL; }
    virtual CASIObjectLoader* getObjectLoader() { return NULL; }
    virtual CASIStatus launchDebugger(char * appli)
        { return CASI_STATUS_NOTSUPPORTED; }

    // Returns the external port map.
    // Currently port export is not fully supported.
    CASIExtPortMap * getExtPortMap(void) { return & extPortMaps; }

    // Define a parameter.
    void defineParameter(const std::string &key, const std::string &value,
                  const CASIParameterProperties *prop = NULL);

protected:
    // Defines a special parameter.
    void defineParameter(const std::string &key, const std::string &value,
        CASIParameterType type, bool is_runtime = true,
        bool is_private = false, bool is_readonly = false,
        const std::string &description="");
public:
    // slaves now know their master
    virtual void connect(CASIClockMasterIF * master);
    virtual void disconnect(CASIClockMasterIF * master);
    virtual CASIClockMasterIF * getMaster() { return clock; }

    // instance names remembered by ports
    virtual void setPortInstanceName(const std::string& name) 
        { casiPortInstanceName = name; }
    virtual std::string getPortInstanceName() 
        { return casiPortInstanceName; }

    // every interface/port has an owner
    virtual void setCASIOwner(CASIModuleIF * owner) 
        { casiOwner = owner; }
    virtual CASIModuleIF * getCASIOwner() { return casiOwner; }

    // ports can be enabled/disabled
    virtual void enablePort(bool enable);
    virtual const bool isPortEnabled();

    // message functions now also available in ports
    virtual void pmessage( const std::string& msg, 
        CASIMessageType type = CASI_MSG_INFO );
    virtual void pmessage( CASIMessageType type, const char *fmt, ... );

    // Return interface if requested 
    virtual CAInterface * ObtainInterface(if_name_t ifName,
            if_rev_t minRev, if_rev_t *   actualRev)
    {
         if((strcmp(ifName,"eslapi.CASIModule2") == 0) && (minRev <= 0))
         {
               *actualRev = 0; 
                return this; 
         }
         return NULL; 
    }

protected:
    CASIClockMasterIF * clock;   // component default master clock
    std::vector<CASIModuleIF*> subcomponents;     // List of children
    CASIParameterMap parameters; // List of component's parameters
    std::string instanceName;    // Name of the instance given at creation time

private:
    CASIModuleIF *parent;           // Direct parent of the component
    std::string instanceID;         // Name of the instance + parents
                                    // ("parent1.parent2.name")
    CASIPortMap ports;              // List of component's port objects
    CASIPortMap thisPorts;          // List of all ports that are this object
    CASIExtPortMap   extPortMaps;   // Map between the external ports and the
                                    // ports of this component
    std::vector<CASIPortArrayIF *> portArrays; // Registered arrays of ports
    bool m_bRegisterClockSlave; // This component will be registered as a
                                    //clock slave during interconnect
                                    // port name & internal port
    bool m_bOptimizedClockSlave;
    CASIPhase phases;
    uint32_t numOfTimes;
    uint32_t ratio;
    uint32_t offset;

    std::string casiPortInstanceName;    // every port knows its instance name
    CASIModuleIF* casiOwner;             // every port knows its owner
    bool casiIsEnabled;                  // ports can be disabled
    bool casiIsConnected;                // whether port is connected to a real
                                // (architectural) port, or left unconnected. 
};