| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0359B |
| Non-Confidential | |
 PDF version | |
| Home > AMBA™ AHB TLM Specification for CASI > AHB control signals > AHB bus state machine |
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| Home > AMBA™ AHB TLM Specification for CASI > AHB control signals > AHB bus state machine |
A typical implementation of an AHB master uses a simple state machine to access the AHB slave:
Start
in the arbitration state and use the requestAccess() and checkForGrant() function
to obtain a lock on the bus to the slave. If the bus is granted
and ready, the address state is entered.
The master issues a read() or write() call
with dummy data to determine the status of the slave. The data state
is entered.
The read() or write() call
is repeated to transfer the actual data. If the data is transferred,
the state returns to arbitration.
If there are multiple slaves connected to an AHB master, or the slaves do not have a fixed memory map, the memory map for the slave components must be created before the AHB master accesses the slaves.
For more information on memory map functions, see The CASITransactionIF interface.
Figure B.1 shows the sequence of calls to perform a single write. In this example, a single wait state has been inserted by the slave during the read data phase.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0359B |
| Non-Confidential | |
| PDF version | |
| Home > AMBA™ AHB TLM Specification for CASI > AHB control signals > AHB bus state machine |