The bus masters connected to the slave ports of the bus should call requestAccess() at the rising and falling edges of the hreq signal and/or on the rising edge of hlock.

The value of hreq is encoded into bit 0 of the address parameter of this function (1 = hreq asserted, 0 = hreq deasserted)

The value of hlock is coded in bit 1 (1 = hlock asserted, 0 = hlock deasserted). The falling edge event of hlock is not handled by this call due to its different timing (it is set during the address stage).

The changed semantics of requestAccess() means that this function is not called if hreq and hlock are asserted and unchanged from the previous cycle. The return value of requestAccess() can be ignored and always return CASI_GRANT_DENIED.

It is possible to deassert hlock by driving an IDLE cycle.

AHB_casi_TSPort::requestAccess(uint64_t address)
{
    assert(portID < owner->max_ports);
    // set the request flag for the respective port ID and lock 
    // (coded in bit 1 (2^1))
    owner->registerRequest(portID, address);
    owner->doUpdate = true;

    return  CASI_GRANT_DENIED;
}