C.1.2. Hardware flow control signals
All of the AXI channels have versions of READY and VALID signals that control the flow
between the master and slave. (The read data channel for example
has RVALID and RREADY.) For systems implemented in
hardware, the handshaking is managed by monitoring the state of READY and VALID on
the rising clock edge as shown in Figure C.2:
Note
Figure C.2 shows READY low until VALID is
high. The VALID and READY signals can, however, go high
in either order. The only requirement for signifying that the transfer
is complete is that both signals are high on the rising edge of the
clock.
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