| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0359B |
| Non-Confidential | |
 PDF version | |
| Home > AMBA® AXI TLM Specification for CASI > Introduction to the CASI TLM for AXI > AXI transfer sequences |
| |||
| Home > AMBA® AXI TLM Specification for CASI > Introduction to the CASI TLM for AXI > AXI transfer sequences |
This section describes the different sequences of events that can occur during AXI read or write operations.
Table C.9 lists the cycles for an example single-word write operation with waits on each channel:
Table C.9. Cycle by cycle activity for a write transaction
| Cycle | cts | status[0:2] | Description |
|---|---|---|---|
| 0 | 0 | CASI_MASTER_WAIT, CASI_MASTER_WAIT, CASI_MASTER_WAIT | No action. AXI slave function driveTransaction() is
not called by AXI master. |
| 1 | 0 | - | Null transaction (optional). Master calls the slave with an empty transaction. This might be used for arbitration. |
| 2 | 0 | CASI_MASTER_READY, CASI_MASTER_WAIT, CASI_MASTER_WAIT | Address transfer. Master calls the slave with
a valid transaction. The slave does not change the status on return
from driveTransaction(). |
| 3 | 0 | CASI_SLAVE_READY, CASI_MASTER_WAIT, CASI_MASTER_WAIT | Master calls the slave again. Slave accepts address by changing status. |
| 4 | 1 | CASI_SLAVE_READY, CASI_MASTER_READY, CASI_MASTER_WAIT | Write data transfer. Master calls slave with a transaction with the data elements filled in. The slave does not change the status on return. |
| 5 | 1 | CASI_SLAVE_READY, CASI_SLAVE_READY, CASI_MASTER_WAIT | Master calls the slave again. Slave accepts data by changing status. |
| 6 | 2 | CASI_SLAVE_READY, CASI_SLAVE_READY, CASI_MASTER_READY | Write response transfer. Slave calls notifyEvent() in
AXI master with the response elements filled in. The master does
not change the status on return. |
| 7 | 2 | CASI_SLAVE_READY, CASI_SLAVE_READY, CASI_MASTER_READY | Slave calls the master again. Master accepts data by changing status. |
| 8 | 0 | CASI_MASTER_WAIT, CASI_MASTER_WAIT, CASI_MASTER_WAIT | No action (optional). If no additional writes
are pending, all of the channels are inactive and driveTransaction() is
not called from master. |
The actual transfer sequence can differ considerably from the sequence shown in Table C.9:
If wait states are not required, the receiving channel
can set CASI_SLAVE_READY before returning rather
than waiting for the next call. For example, cycle 3 can be combined
with cycle 2.
The write address and write data can be valid in the same cycle.
For cycle 2 in Table C.9, if the first three elements of the status array
were CASI_MASTER_READY, CASI_MASTER_READY, CASI_MASTER_WAIT,
the slave could accept both of these elements and set the array
contents to CASI_SLAVE_READY, CASI_SLAVE_READY, CASI_MASTER_WAIT on
return.
Cycles 4 and 5 transfer a single word. If a burst-write
operation is occurring, multiple cycles are required for the transfer.
For a burst operation, the number of transaction steps (nts)
is larger.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0359B |
| Non-Confidential | |
| PDF version | |
| Home > AMBA® AXI TLM Specification for CASI > Introduction to the CASI TLM for AXI > AXI transfer sequences |