The PCAPT registers are listed in Table 4.5.
Table 4.5. Pin Capture registers
| Name | Address | Description |
|---|---|---|
| - | 0x3F200000 to 0x3F20005C | Reserved. |
| ASYNCVIC | 0x3F200070 | Reads the value of the ASYNCVIC control signal and enables writing of a new value pending a system reset. See ASYNCVIC. |
| ClkCtl | 0x3F200080 | Controls Clock divider division values. See ClkCtl. |
| ClkEnCtl | 0x3F200084 | Controls Clock divider division values and clock sources. See ClkEnCtl. |
| - | 0x3F200100 to 0x3F200114 | Reserved. |
| ETMCtl | 0x3F20011C | Controls the source of ETMEXTINX to the ETM. See ETMCtl |
| - | 0x3F200118 | Reserved. |
| IEMCtl | 0x3F200090 | Reads the SYNCMODEACK outputs and allows the SYNCMODEREQ inputs to the ARM1176JZF-S to be controlled. See IEMCtl. |
| TRUSTZONENSA | 0x3F2000A0 | Controls whether non-secure accesses made to the peripherals are permitted. See TrustZone Control Registers |
| TRUSTZONESD | 0x3F2000B0 | Controls whether secure accesses made to the peripherals are denied. See TrustZone Control Registers |
| TC-Control | 0x3F2000C0 | Controls a number of features of the ARM1176JZF-S test chip. See TC-Control. |
| - | 0x3F2000D0 | Reserved. |
| BLKDISABL | 0x3F2000E0 | Controls the memory map decoders in the AXI bus matrix. Enables peripherals to be removed from the memory map and the released memory space to be redirected to the external AXI interface. See BLKDISABL. |
| − | 0x3F200200 to 0x3F2FFFFF | Reserved. |
The ASYNCVIC register allows setting and reading of ASYNCVIC that is used to drive the VIC interface signals IRQADDRVSYNCEN, INTSYNCEN and nVICSYNCEN. See ARM PrimeCell Vectored Interrupt Controller Technical Reference Manual (PL192) (DDI 0273) for details of the VIC port connections. By default, out of reset, this signal is driven HIGH to enable asynchronous interfaces. By writing to register bit [0] the state of the signal can be changed. Writes are held pending until the next system reset. Register bit [1] always reflects the actual state of ASYNCVIC and will only change after a system reset.
This register is located at PCAPTBASE+0x70 as
follows:
Address [31:0]=0x3F200070
Reset by: nPORESETX (power-on reset).
Figure 4.2 shows the ASYNCVIC register bit assignments.
Table 4.6 describes the ASYNCVIC register fields.
Table 4.6. ASYNCVIC register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:4] | Read only | - | 0x0000000 | Unused |
| [3:2] | Read only | - | b00 | Unused |
| [1] | Read only | ASYNCVIC | b1 | Reads the value of the ASYNCVIC control signal being driven to ARM1176JZF-S processor and VIC |
| [0] | Read/Write | NewASYNCVIC | b1 | Write new value for the ASYNCVIC control signal, to be driven at next system reset |
The ClkCtl, and ClkEnCtl clock registers control clock distribution in the ARM1176JZF-S test chip and are described in Clocks.
The ETM Control Register selects the input sources for the CoreSight ETM11 EXTIN[3:0] bus.
This register is located at PCAPTBASE+0x11C as
follows:
Address [31:0]=0x3F20011C
Reset by: nRESETX (system reset).
Figure 4.4 shows the ETMCtl register bit assignments.
Table 4.7 describes the ETMCtl register fields.
Table 4.7. ETMCtl register bit assignments
| Bits | Access | Name | Reset Value | Description |
|---|---|---|---|---|
| [31:6] | Read/Write | - | SBZ/UNP | Unused |
| [5:0] | Read/Write | EtmInputSel | b000000 | Selects input sources for the ETM11:
|
The IEMCtl register allows the IEM register slices SYNCMODEREQ inputs to be controlled and the SYNCMODEACK outputs to be read. There are also bits that allow pseudo-random strobing of SYNCMODEREQ. This can only be enabled when the corresponding SYNCMODEREQ control bit is set.
This register is located at PCAPTBASE+0x90 as
follows:
Address [31:0]=0x3F200090
Reset by: nPORESETX (power-on reset).
Figure 4.4 shows the IEMCtl register bit assignments.
Table 4.8 describes the IEMCtl register fields.
Table 4.8. IEMCtl register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:12] | Read as zero, write ignored. | - | 0x00000 | Undefined. |
| [11] | Read/Write | SYNCMODEREQP- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the P-port IEM register slice. At pseudo-random times SYNCMODEREQP is toggled and then waits for SYNCMODEACKP before toggling again. |
| [10] | Read/Write | SYNCMODEREQD- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the D-port IEM register slice. At pseudo-random times SYNCMODEREQD is toggled and then waits for SYNCMODEACKD before toggling again. |
| [9] | Read/Write | SYNCMODEREQRW- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the RW-port IEM register slice. At pseudo-random times SYNCMODEREQRW is toggled and then waits for SYNCMODEACKRW before toggling again. |
| [8] | Read/Write | SYNCMODEREQI- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the I-port IEM register slice. At pseudo-random times SYNCMODEREQI is toggled and then waits for SYNCMODEACKI before toggling again. |
| [7] | Read only | SYNCMODEACKP | b0 | When HIGH indicates that the P-port IEM register slice has transitioned to synchronous mode |
| [6] | Read only | SYNCMODEACKD | b0 | When HIGH indicates that the D-port IEM register slice has transitioned to synchronous mode |
| [5] | Read only | SYNCMODEACKRW | b0 | When HIGH indicates that the RW-port IEM register slice has transitioned to synchronous mode |
| [4] | Read only | SYNCMODEACKI | b0 | When HIGH indicates that the I-port IEM register slice has transitioned to synchronous mode |
| [3] | Read/Write | SYNCMODEREQP | SYNCMODEREQD/P-init | IEM register slice control for the ARM1176JZF-S P-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
| [2] | Read/Write | SYNCMODEREQD | SYNCMODEREQD/P-init | IEM register slice control for the ARM1176JZF-S D-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
| [1] | Read/Write | SYNCMODEREQRW | SYNCMODEREQI/RW-init | IEM register slice control for the ARM1176JZF-S RW-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
| [0] | Read/Write | SYNCMODEREQI | SYNCMODEREQI/RW-init | IEM register slice control for the ARM1176JZF-S I-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
Note
The Table 4.18 holds the progammable Reset values.
There are two TrustZone control registers:
TRUSTZONENSA
TRUSTZONESD
The two TrustZone Control Registers control the security policy
that is applied to accesses to the various peripherals on the ARM1176JZF-S test
chip. With both registers set to 0x0, only secure
accesses to the various peripherals are permitted. All non-secure accesses
return an error.
Setting bits in TRUSTZONENSA enables non-secure accesses to the peripherals. Setting bits in TRUSTZONESD denies secure access to the peripherals (this is not intended to reflect typical usage of TrustZone memory controls).
Note
By setting bits in TRUSTZONESD, and clearing them in TRUSTZONENSA, you can deny all accesses to a peripheral.
The TRUSTZONESD register is contained within the pin capture block. If accesses to the pin capture block are denied, subsequent writes to this register are not possible. That is, you cannot re-enable accesses to the pin capture block.
TRUSTZONENSA is located at PCAPTBASE+0xA0 as
follows:
Address [31:0]=0x3F2000A0
Reset by: nPORESETX (power-on reset).
Figure 4.5 shows the TRUSTZONENSA register bit assignments.
Table 4.9 describes the TRUSTZONENSA register fields.
Table 4.9. TRUSTZONENSA register
| Bit | Access | Reset value | Peripheral |
|---|---|---|---|
| [31:8] | Read only | 0x000000 | Unused |
| [7] | Read only | b1 | Unused |
| [6] | Read/Write | TRUSTZONENSA-init | RAM2 memory |
| [5] | Read/Write | TRUSTZONENSA-init | Test chip RAM |
| [4] | Read/Write | b1 | Unused |
| [3] | Read/Write | TRUSTZONENSA-init | Unused |
| [2] | Read/Write | TRUSTZONENSA-init | Pin capture block |
| [1] | Read/Write | TRUSTZONENSA-init | ETM |
| [0] | Read/Write | TRUSTZONENSA-init | VIC |
TRUSTZONESD is located at PCAPTBASE+0xB0 as
follows:
Address [31:0]=0x3F2000B0
Reset by: nPORESETX (power-on reset).
Figure 4.6 shows the TRUSTZONESD register bit assignments.
Table 4.10 describes the TRUSTZONESD register fields.
Table 4.10. TRUSTZONESD register
| Bit | Access | Reset value | Peripheral |
|---|---|---|---|
| [31:8] | Read only | 0x000000 | Unused |
| [7] | Read only | b0 | Unused |
| [6] | Read/Write | TRUSTZONESD-init | RAM2 memory |
| [5] | Read/Write | TRUSTZONESD-init | Test chip RAM |
| [4] | Read/Write | b0 | Unused |
| [3] | Read/Write | TRUSTZONESD-init | Unused |
| [2] | Read/Write | TRUSTZONESD-init | Pin capture block |
| [1] | Read/Write | TRUSTZONESD-init | ETM |
| [0] | Read/Write | TRUSTZONESD-init | VIC |
The TC-Control register controls a number of the features of the ARM1176JZF-S test chip.
This register is located at PCAPTBASE+0xC0 as
follows:
Address [31:0]=0x3F2000C0
Reset by: nPORESETX (power-on reset).
Figure 4.7 shows the TC-Control register bit assignments.
Table 4.11 describes the TC-Control register fields.
Table 4.11. TC-Control register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:4] | Read as zero, write ignored. | - | 0x0000000 | Undefined |
| [3:2] | Read as zero, write ignored. | - | b00 | Undefined |
| [1] | Read/Write | ForceETMPWRUP | b0 | When HIGH forces ETMPWRUP (ETM powered up indicator) to the ARM1176JZF-S HIGH |
| [0] | Read/Write | EnableVIC | b0 | When HIGH connects interrupt inputs nIRQ and nFIQ via the VIC |
The BLKDISABL register controls the memory map decoders in the AXI bus matrix. By setting the appropriate register bit each of the peripherals can be removed from the memory map and the memory space automatically re-allocated to the external AXI interface. When all the register bits are set, all memory accesses are routed to the external AXI interface.
When you set the Test chip RAM remap bit, the test chip memory
(RAM0 and RAM1) appears at address 0x0, in addition
to address 0x3F800000. This is independent of
the test chip RAM disable control.
Caution
This register is implemented within the pin capture block. If the pin capture block is disabled, further writes to this register will not be possible and it will not be possible to re-enable the pin capture block.
This register is located at PCAPTBASE+0xE0 as
follows:
Address [31:0]=0x3F2000E0
Reset by: nPORESETX (power-on reset)
Figure 4.8 shows the BLKDISABL bit assignments.
Table 4.12 describes the BLKDISABL register fields.
Table 4.12. BLKDISABL register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:8] | Read as zero, write ignored. | - | 0x000000 | Undefined |
| [7] | Read/Write | TCRAM | BLKDISABL-init[7] | Test chip RAM disable |
| [6] | Read/Write | ETM | BLKDISABL-init[6] | ETM disable |
| [5] | Read/Write | - | b0 | Unused |
| [4] | Read/Write | PCAPT | BLKDISABL-init[4] | Pin Capture block disable |
| [3] | Read/Write | VIC | BLKDISABL-init[3] | VIC disable |
| [2] | Read/Write | RAM2 | BLKDISABL-init[2] | RAM2 memory disable |
| [1] | Read/Write | SPARE/DUMMY | BLKDISABL-init[1] | SPARE/DUMMY region disable |
| [0] | Read/Write | REMAP-init | REMAP-init | Test chip RAM remap |
Note
The Config-init register holds the progammable reset values.
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