Core Tile for ARM1176JZF-S™ User GuideHBI-0154
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4.2. Memory map

The address map of the ARM1176JZF-S test chip is shown in Table 4.1.

Note

Peripherals are multiple mapped throughout their allocated address range.

Each of the peripherals may be disabled by programming the BLKDISABL register. Any access to a disabled peripheral is redirected to the external AXI interface. See Block disables and Pin capture block for further information on the BLKDISABL register.

Table 4.1. ARM1176JZF-S test chip address map

BlockAddressSizeDescription
EXT_AXI_10x00000000 to 0x3EFFFFFF1008MBAccess to external AXI port.
Dummy0x3F000000 to 0x3F07FFFF512KBDummy slave. Generates AXI SLVERR error responses. Can be disabled.
Spare0x3F080000 to 0x3F0FFFFF512KBSpare region. Generates AXI DECERR error responses. Can be disabled.
AHBVIC0x3F100000 to 0x3F1FFFFF1MBControl port for vectored interrupt controller (VIC).
PCAPT0x3F200000 to 0x3F2FFFFF1MBPin capture and TZ control.
Reserved0x3F300000 to 0x3F37FFFF512KBReserved memory space.
Reserved0x3F380000 to 0x3F3FFFFF512KBReserved memory space.
ETM0x3F400000 to 0x3F4FFFFF1MBETM control port.
External0x3F500000 to 0x3F5FFFFF1MBRecommended for IEM components.
External0x3F600000 to 0x3F6FFFFF1MBRecommended for Level 2 cache controller.
AHBRAM0x3F700000 to 0x3F7FFFFF1MBSRAM, 16KB, wrapped.
AXIRAM10x3F800000 to 0x3FFFFFFF4MB maxSRAM, interleaved on 1KB boundaries with AXIRAM0 and wrapped.
AXIRAM00x3F800000 to 0x3FFFFFFF4MB maxSRAM, interleaved on 1KB boundaries with AXIRAM1 and wrapped.
EXT_AXI_20x40000000 to 0xCF1FFFFF2290MBExternal AXI access.
Reserved0xCF200000 to 0xCF2FFFFF1MBReserved memory space.
Reserved0xCF300000 to 0xCF3FFFFF1MBReserved memory space.
ETM0xCF400000 to 0xCF4FFFFF1MBETM control registers.
EXT_AXI_30xCF500000 to 0xFFFFFFFF779MBExternal AXI access.
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