RealView ® LT-XC5VLX330 UserGuideLogic Tile HBI-0172
Home

RealView ® LT-XC5VLX330 UserGuide

Logic Tile HBI-0172

Copyright © 2007 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this document
Intended audience
Organization
Typographical conventions
Further reading
Feedback
Feedback on the baseboard
Feedback on the RealView LT-XC5VLX330 Logic Tile
1. Introduction
1.1. About the LT-XC5VLX330 Logic Tile
1.2. Logic Tile architecture
1.3. Precautions
1.3.1. Ensuring safety
1.3.2. Preventing damage
2. Getting Started
2.1. Using the Logic Tile with an InterfaceModule or with a baseboard
2.2. Switches and LEDs
2.2.1. Switches
2.2.2. LEDs
2.3. Using RealView ICE or other JTAG equipment
3. Hardware Description
3.1. FPGA
3.1.1. FPGA I/O arrangement
3.1.2. JTAG and the FPGA
3.1.3. FPGA Configuration from flash memory
3.2. Header signals
3.2.1. Variable I/O levels
3.2.2. Foldover
3.3. Clock architecture
3.3.1. Onboard programmable clock generators
3.3.2. Global clock
3.3.3. Retimed clocks on multiple tiles
3.3.4. Delay-matched clock distribution (2up / 2 down)
3.4. Reset control
3.5. Memory system
3.5.1. Flash memory
3.5.2. SRAM Memory
3.6. JTAG support
4. Configuring the FPGA
4.1. Configuration system architecture
4.1.1. Debug mode
4.1.2. Configuration mode
4.2. FPGA tool flow
4.2.1. Synthesis
4.2.2. Place and route
4.3. Configuring the FPGA from flash
4.3.1. Downloading new FPGA configurations to flash memory
4.4. Reconfiguring the FPGA directly
4.4.1. Downloading an image directly to theFPGA
4.4.2. Using Xilinx download tools
A. Pinouts and Specifications
A.1. Header connectors
A.1.1. HDRX
A.1.2. HDRY
A.1.3. HDRZ
A.2. Electrical specification
A.2.1. Bus interface characteristics
A.2.2. Current requirements
A.3. Mechanical details

List of Figures

1.1. LT-XC5VLX330 layout (heatsink not shown)
1.2. System architecture
2.1. Standalone operation with processorin FPGA
2.2. Logic Tile mounted on a PB926EJ-S
2.3. Logic Tile and Core Tile mountedon an EB
2.4. Switches and LEDs
3.1. LT-XC5VLX330 block diagram
3.2. LT-XC5VLX330 top and bottom headerconnections
3.3. Flash memory programming
3.4. Timing sequence for loading the FPGAimage from flash
3.5. Simplified view of foldover and thrusignals
3.6. Two tile foldover example
3.7. Three tile foldover example
3.8. Clock signal overview
3.9. Programmable clock generators
3.10. VCO configuration data
3.11. Global clock source selection
3.12. Retimed clocking scheme
3.13. Clock retiming using a DLL
3.14. Retimed clock routing for three tiles(from bottom tile)
3.15. Retimed clock routing for three tiles(from middle tile)
3.16. Delay-matched clocking scheme
3.17. Delay-matched clocks for five tiles
3.18. Power-on reset sequence
3.19. Reset and configuration control
3.20. Memory system
3.21. JTAG data paths
3.22. JTAG clock paths
3.23. JTAG TMS paths
4.1. Configurationsystem architecture
4.2. Reconfigure sequence
4.3. Basic tool flow for building FPGAimages
A.1. HDRX, HDRY, and HDRZ (upper) pinnumbering
A.2. Board outline

List of Tables

1.1. Comparison of Virtex-II, Virtex-4, and Virtex-5 Logic Tiles
3.1. I/O pin distribution
3.2. Virtex-5 FPGA external clocks
3.3. Virtex-5 resets
3.4. Virtex-5 FPGA JTAG
3.5. FPGA I/O bank signal level
3.6. HDRX upper foldover connection
3.7. HDRX lower foldover connection
3.8. HDRY upper foldover connection
3.9. HDRY lower foldover connection
3.10. HDRZ upper foldover connection
3.11. HDRZ lower foldover connection
3.12. ICS307M-02 OD settings
3.13. Reset signal descriptions
4.1. Image selection for XC5V FPGAs
A.1. HDRX signals
A.2. HDRY signals
A.3. HDRZ signals
A.4. Electrical characteristics for 3.3V I/O
A.5. Current requirements
A.6. Samtec part numbers
A.7. Samtec part number and mating heights

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited, except as otherwise stated below in this proprietarynotice. Other brands and names mentioned herein may be the trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt frompart 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Logic Tile generates, uses, and can radiate radio frequencyenergy and may cause harmful interference to radio communications.However, there is no guarantee that interference will not occurin a particular installation. If this equipment causes harmful interferenceto radio or television reception, which can be determined by turningthe equipment off or on, you are encouraged to try to correct theinterference by one or more of the following measures:

  • ensure attached cables donot lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment andthe receiver

  • connect the equipment into an outlet on a circuitdifferent from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technicianfor help

Note

It is recommended that wherever possible shielded interfacecables be used.

Revision History
Revision A July2007 First release
Revision B October2007 Enhancement to text
Copyright © 2007 ARM Limited. All rights reserved. ARM DUI 0365B
PDF file icon   PDF version
Home