The term system and component are both used to describe the output from System Canvas. The main difference is whether the output is intended as a standalone system or is to be used within a larger system.

Figure 1.3 shows the advantage of using a hierarchical system with a complex model. This system includes a Secure ARM1176JZ-S™ Core Tile and an Emulation Baseboard.

Figure 1.3. EB_1176 system

The central component in the system is a EmulationBaseboard component. Open this item by selecting it and selecting Open Component from the Object menu. Figure 1.4 shows that it is a complex object with many subcomponents:

Figure 1.4. EmulationBaseboard component

Hiding the complexity of the Emulation Baseboard in a component simplifies the drawing shown in Figure 1.3 and also enables the Emulation Baseboard component to be maintained separately from the ARM1176 Core Tile component. The Emulation Baseboard component communicates with components in the higher-level system through its self ports. The clock dividers in the Clocking component at the top-left of the diagram show a connection to an external port called clk_in_master. Opening a clock divider component to see the LISA code. The Block Diagram window shows the external ports for that subcomponent, see Figure 1.5.

Figure 1.5. Clock divider component external ports

The clock divider component contains only external ports. There are no subcomponents. The behavior for this component is determined by the LISA code and, if present, the C++ code. Only two ports are shown for the clock divider in Figure 1.4 because the rate port is hidden. There is no connection to this port. The port itself can be unhidden by selecting the component and selecting Show all ports from the context menu.

The term self port refers to a port in a system that is not part of a subcomponent. In Figure 1.4, self ports are represented by hollow rectangles with triangles to indicate data flow and a text label in the rectangle. Examples include keyboard, mouse and hdr. Self ports can be either:

If you use the Block Diagram editor to make a connection between an external port and a subcomponent, the LISA code uses the keyword self to indicate the standalone port:

self.clk_in_master => clkdiv_ref25.clk_in;