This example, shown in Figure 5.7, is a modified version of the PV example from the OSCI TLM 2.0 package.
The Cortex R4 programs a transfer and waits for an interrupt signaled by the PV DMA from the SystemC side to indicate the transfer is complete.
The Fast Models system contains the following components:
Cortex R4CPUPVBusDecoderRAMDevicefor the application memoryPVBus2AMBAPVbridge to the SystemC sideAMBAPVSignal2SGSignalbridge to forward end of transfer interrupts from SystemC into Fast ModelsSGSignal2AMBAPVSignalbridge to forward the end of transfer interrupts from Fast Models back into SystemC.AMBAPV2PVBusbridge from the SystemC sideDMAtransfer source memory.
The SystemC side contains:
Simple PV DMA model
Associated source and destination memories
Pseudo master to receive end of transfer interrupt from Fast Models.
The project file is $PVLIB_HOME/examples/SystemCExport/DMA/Build/DMA.sgproj.
To build the debug version of the example, enter the following at the command line:
cd $PVLIB_HOME/examples/SystemCExport/DMA/Build
make DEBUG=y clean all
To build the release version of the example, enter the following at the command line:
cd $PVLIB_HOME/examples/SystemCExport/DMA/Build
make DEBUG=n clean all
Note
The make clean command is optional. If
used, the model is completely rebuilt.
To build the debug version of the example, enter the following at the command line:
cd %PVLIB_HOME%\examples\SystemCExport\DMA\Build
build_Windows-Debug-vc_version.bat
where vc_versionVC2005 or VC2008 as
appropriate to select the batch file that corresponds to the Windows
compiler being used.
To build the release version of the example, enter the following at the command line:
cd %PVLIB_HOME%\examples\SystemCExport\DMA\Build
build_Windows-Release-vc_version.bat
where vc_versionVC2005 or VC2008 as
appropriate to select the batch file that corresponds to the Windows
compiler being used.
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