Fast Models User Guide

Version 7.0

Table of Contents

About this book
Intended audience
Using this book
Typographical conventions
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About Fast Models
1.1.1. Software requirements
1.1.2. Installation and uninstallation
1.2. Fast Models design flow
1.2.1. Project and repository files
1.2.2. Hierarchical systems
2. Getting Started
2.1. About the tutorial
2.2. Starting System Canvas
2.2.1. Setting up the Fast Model Portfolio
2.3. Creating a sample system
2.4. Adding and configuring components
2.4.1. Adding the ARM processor
2.4.2. Naming components
2.4.3. Hiding ports
2.4.4. Moving ports
2.4.5. Resizing components
2.4.6. Adding additional components
2.4.7. Using port arrays
2.5. Connecting components
2.6. Fast Models files
2.6.1. LISA source
2.6.2. System Canvas file
2.6.3. Fast Models project file
2.7. Viewing the project settings
2.7.1. Specifying the Project Active Configuration
2.7.2. Viewing the top component properties
2.8. Changing the address mapping
2.9. Building the system
2.10. Debugging the system
2.11. Building an ISIM target
2.11.1. Overloading the main() function in the target
2.11.2. Command line switches for the executable target
2.12. Setting-up a network connection and configuring the networking environment for Microsoft Windows
2.12.1. Setting-up a network connection
2.12.2. Configuring the networking environment
2.12.3. Usage of tap_setup_32.exe or tap_setup_64.exe
2.12.4. Uninstalling
2.13. Setting-up a network connection and configuring the networking environment for Linux
2.13.1. Setting-up a network connection
2.13.2. Configuring the networking environment
2.13.3. Disabling and re-enabling networking
2.13.4. Uninstalling networking
3. Debugging
3.1. About debugging
3.2. Debugging from System Canvas
3.2.1. Configuring Model Debugger
3.2.2. Using RealView Debugger
3.3. Batch mode debugging
3.3.1. Direct execution
3.3.2. Debug server
3.4. Using other debuggers to debug LISA source
3.4.1. Model generation requirements
3.4.2. Debugging with GDB
3.4.3. Debugging with Microsoft Visual Studio
3.5. Working with the ARM Profiler
3.5.1. ARM Profiler on Microsoft Windows workstation
3.5.2. ARM Profiler on Linux Workstation
3.5.3. Running ARM Profiler
3.5.4. Running the ARM profiler with Dhrystone example
4. System Canvas Reference
4.1. Launching System Canvas
4.2. Overview of System Canvas
4.2.1. Menu bar
4.2.2. Toolbar
4.2.3. Workspace windows
4.2.4. Component window
4.2.5. Output window
4.3. Add Existing Files and Add New File dialogs (Component window)
4.3.1. Using environment variables in filenames
4.3.2. Assigning libraries and compiler option for platforms
4.4. Add Files (Project menu)
4.5. Add Connection dialog
4.6. Component Instance Properties dialog
4.6.1. Component Model Properties dialog for system
4.7. Component Properties dialog for a library component
4.8. Connection Properties dialog
4.9. Edit Connection dialog
4.10. File/Path Properties dialog
4.11. Find and Replace dialogs
4.12. Label Properties dialog
4.13. New File dialog (from File menu)
4.14. New Project dialogs
4.14.1. Select Top Component LISA File dialog
4.15. Open File dialog
4.16. Port Properties dialog
4.17. Preferences dialog
4.17.1. Appearance
4.17.2. Applications
4.17.3. External Tools
4.17.4. Fonts
4.17.5. Default Model Repository
4.17.6. Suppressed Messages
4.18. Project Settings dialog
4.18.1. Project top-level settings
4.18.2. Parameters category
4.18.3. Alphabetical list of project parameter IDs
4.18.4. Project file contents
4.19. Protocol Properties dialog
4.20. Run Dialog
4.21. Self Port dialog
5. SystemC Export
5.1. About SystemC export
5.2. Building a SystemC component from System Canvas
5.2.1. Installing SystemC and TLM files
5.2.2. Building the EVS
5.2.3. Adding header files and libraries for Linux export
5.2.4. Adding header files and libraries for Microsoft Windows export
5.3. Adding the generated SystemC component to a SystemC system
5.4. Using the generated ports
5.4.1. Protocol definition
5.4.2. Properties for TLM1.0 based protocols
5.4.3. Properties for TLM 2.0 based protocols
5.5. Example systems
5.5.1. Building Example systems
5.5.2. Running the Example system
5.5.3. Running the examples with debug support
5.5.4. Dhrystone example
5.5.5. Dhrystone2 example
5.5.6. DMA example
5.5.7. EVS_Callbacks_Cortex-R4 example
5.5.8. Linux Example
5.5.9. Protocols example
5.5.10. EVS_Delay_Cortex-A8 Example
5.6. SystemC component API
5.6.1. Component access function
5.6.2. Parameter access functions
5.6.3. Simulation control functions
5.6.4. Application loading functions
5.6.5. Debug control functions
5.6.6. Accessing the CADI interface directly
5.7. Scheduling of Fast Models and SystemC
5.7.1. Standalone simulation without a debug server
5.7.2. Simulation with a debug server
5.8. Limitations
5.8.1. Single SC_THREAD and wait() calls
5.8.2. Single SC_THREAD and problems with re-entrancy
5.8.3. Calling wait() in the middle of a transaction
5.8.4. Timing annotation
5.8.5. Code translation support for external memory
5.8.6. Debug accesses
6. Creating a New Component
6.1. Basic configuration
6.1.1. Create a new LISA file
6.1.2. Resources section
6.2. Adding ports
6.3. Behavior section
6.3.1. View the SerialData protocol
6.3.2. Adding the new behavior to the SerialCharDoubler slave port
6.3.3. Master port
6.3.4. Special purpose behaviors
6.4. Using the SerialCharDoubler component in the system
A. Building and Running the EB RTSM Example System
A.1. Using System Canvas to build the platform model
A.1.1. Building an EB Real-Time System Model
A.1.2. Packaging the system model for distribution
A.2. Connecting to the model
A.2.1. Using Model Shell to run the system model
A.2.2. Using Model Debugger to run a system model
A.2.3. Using RealView Debugger to run a system model
A.3. Running an application on the system model
A.3.1. Running the brot application in Model Debugger
A.3.2. Running the brot application in RealView Debugger
A.3.3. Using the CLCD window
B. Red Hat Linux Dependencies
B.1. About dependencies
B.2. Dependencies for Red Hat Enterprise Linux 4
B.3. Dependencies for Red Hat Enterprise Linux 5
C. Building System Models in Batch Mode
C.1. Introduction
C.2. SIMGEN command-line options
C.2.1. Using command-line options to decrease compilation time
C.2.2. Interaction between num-comps-file and num-build-cpus
C.2.3. Setting command-line parameters from System Canvas

List of Figures

1.1. Fast Models design flow
1.2. Project organization
1.3. Block diagram of top-level VE model in System Canvas
1.4. Contents of VE motherboard component
1.5. Self port detail
1.6. Clock divider component external ports
2.1. System Canvas at startup
2.2. Preferences dialog, Setup Default Model Repository
2.3. Add Model Repository File dialog
2.4. New project dialog
2.5. Select Top Component LISA File dialog
2.6. ARMCortexA8CT core component in the Block Diagram window
2.7. Rename component
2.8. Processor component after changes
2.9. Port context menu
2.10. Example system with added components
2.11. Connected components
2.12. Project settings for the example
2.13. Select Top Component dialog showing available components
2.14. Viewing the address Mapping from the Port Properties dialog
2.15. Edit Connection dialog
2.16. Edit address map for slave port
2.17. Build process output
2.18. Project Settings dialog
2.19. Debug Simulation dialog
2.20. Configuring Model Parameters dialog
2.21. Select Targets dialog
2.22. Model Debugger Application Input window
2.23. Build Integrated Simulator target
2.24. Specifying user-defined main() option
3.1. Debug Simulation dialog
3.2. Configure Model Parameters dialog
3.3. Select Targets dialog
3.4. Load application for core
3.5. Dual core system running in Model Debugger
3.6. Model Debugger paths in the Preferences dialog
3.7. Direct execution use case
3.8. Debug server use case
4.1. Layout of System Canvas
4.2. Add New File dialog
4.3. Add Existing Files dialog
4.4. Add Files dialog
4.5. Add Connection dialog
4.6. Component Instance Properties dialog, General tab
4.7. Component Instance Properties dialog, Properties tab
4.8. Component Instance Properties dialog, Parameters tab
4.9. Component Instance Properties dialog, Ports tab
4.10. Component Instance Properties dialog, Methods tab
4.11. Component Model Properties dialog
4.12. Component Model Properties dialog, Properties tab
4.13. Component Model Properties dialog, Parameters tab
4.14. Add Component Parameter dialog
4.15. Component Model Properties dialog, Ports tab
4.16. Component Properties dialog for SerialCharDoubler
4.17. Component Properties dialog, Properties tab
4.18. Component Properties dialog, Parameters tab
4.19. Component Properties dialog, Ports tab
4.20. Component Properties dialog, Methods tab
4.21. Connection Properties dialog
4.22. Add/Edit Connection Mapping dialog
4.23. File/Path Properties dialog, General tab
4.24. File/Path Properties dialog, Build actions tab
4.25. Find dialog
4.26. Find and Replace dialog
4.27. Label Properties dialog
4.28. New File dialog
4.29. New Project dialog
4.30. Select Top Component LISA File dialog
4.31. Open File dialog
4.32. Port Properties dialog
4.33. Preferences dialog
4.34. Preferences dialog, Applications
4.35. Preferences, Applications for Linux
4.36. Preferences dialog, External Tools
4.37. Preferences dialog, Fonts
4.38. Preferences dialog, Model Repository
4.39. Add Model Repository File
4.40. Preferences dialog, Suppressed Messages
4.41. Project Settings dialog
4.42. Project Settings dialog, Category View top level
4.43. Project Settings dialog, Category View Targets
4.44. Project Settings dialog, Category View Debugging
4.45. Project Settings dialog, Category View Sim Generator
4.46. Project Settings dialog, Category View Compiler
4.47. Project Settings dialog, Category View Linker
4.48. Project Settings dialog, List View
4.49. Project Settings dialog, Tree View
4.50. Protocol Properties dialog for SerialData
4.51. Run Dialog
4.52. Self Port dialog
5.1. Scheduling between Fast Models and SystemC domains
5.2. Port wrappers connect Fast Models and SystemC components
5.3. SGSignal component in System Canvas
5.4. CADI client and server connects Model Debugger and system
5.5. Dhrystone system example
5.6. Dhrystone2 system example
5.7. DMA system example
5.8. Linux example
5.9. Protocols example
5.10. Reset Example system
5.11. Timing diagram for driving the reset signal
5.12. Yield equation
5.13. Simulation without a debug server
5.14. Standalone simulation with a debug server
5.15. SC_THREAD wrapper for exported components
5.16. Blocking transactions in single SC_THREAD
5.17. Calling wait() in the middle of a transaction
5.18. Transaction issued by EVS
5.19. Transaction issued by SystemC
5.20. Local modification of external memory
5.21. Debug accesses from a SystemC component
6.1. Character doubler component
6.2. Self Port dialog
6.3. Select Protocol dialog
6.4. SerialCharDoubler inserted in dual core system
6.5. Linux booting with SerialCharDoubler component
A.1. Model Debugger Connect remote dialog
A.2. Model Debugger Select Targets dialog
A.3. Configure Model Parameters dialog
A.4. CLCD window
A.5. Breakpoint in brot.c
A.6. CLCD window at startup
A.7. CLCD window alternative display

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AAugust 2007New document.
Revision BDecember 2007Release 3.1.
Revision CFebruary 2008Release 3.2.
Revision DJune 2008Update for System Generator 4.0.
Revision EAugust 2008Update for System Generator 4.0 SP1.
Revision FDecember 2008Update for Fast Models 4.1.
Revision GMarch 2009Update for Fast Models 4.2. New SystemC and TLM 2.0 features.
Revision HApril 2009Update for Fast Models 5.0.
Revision ISeptember 2009Update for Fast Models 5.1.
Revision JFebruary 2010Update for Fast Models 5.2.
Revision KOctober 2010Update for Fast Models 6.0.
Revision LMay 2011Update for Fast Models 6.1.
Revision MNovember 2011Update for Fast Models v7.0.
Copyright © 2007-2011 ARM. All rights reserved.ARM DUI 0370M