The terms system and component are both used to describe the output from System Canvas. The
main difference is whether the output is intended as a standalone system or is to be used
within a larger system.
The block diagram shows the advantage of using a hierarchical system with a complex model.
This system includes a Cortex-A15 CoreTile and a VE motherboard and daughterboard.
Figure 1-3 Block diagram of top-level VE model
in System Canvas
The central component in the system is a VE motherboard component. To open this item,
select it and select Open Component from the
Object menu. It is a complex object with many subcomponents.
Figure 1-4 Contents of VE motherboard component
Hiding the complexity of the VE motherboard in a component simplifies the drawing and
enables the VE motherboard component to be shared between different FVP models.
For example, the clockdivider component located at the top-left of of the contents diagram
has a connection to an external port called
Figure 1-5 Self port detail
By double-clicking a component, in this case a clock divider, you can open it to see the
LISA code, and the resulting Block Diagram window displays the external ports for that
Figure 1-6 Clock divider component external ports
The clock divider component contains only external ports, and it has no subcomponents. The
behavior for this component is determined by the LISA code and, if present, the C++ code.
Only two ports are shown for the clock divider in the self port detail figure because the
rate port is hidden. To display this port, right-click the component and
select Show all ports from the context menu. There is no connection
A component communicates with components in the higher-level
system through its self ports. Self ports refer
to ports in a system that are not part of a subcomponent, and are
represented by a hollow rectangle with triangles to indicate data
flow, and a text label in the rectangle.
Self ports can be internal or external.
- Internal ports
These ports communicate with subcomponents and are
not visible if the component is used in a higher-level system. Unlike
hidden external ports, you cannot expose internal ports outside
the subcomponent. Right-click on a port and select Object
Properties... to identify or create internal ports.
Set the port attributes to Internal for an
internal self port.
- External ports
These ports communicate with components in a higher-level
system, and by default are external.
If you use the Block Diagram editor to make a connection between
an external port and a subcomponent, the LISA code uses the keyword self to indicate
the standalone port:
self.clk_in_master => clkdiv_ref25.clk_in;