2.6. Port declarations

Communication between components is done with master and slave ports using Transaction Level Modeling (TLM). The ports use standard or user-defined protocols to communicate between components. Read and write accesses are always initiated from master ports.

The cores use this interface style to communicate with the peripherals. It can also be used for communication between peripherals. The communication connections are defined in the connection section of each component. See Connection section.

This kind of communication encapsulates each component behind an abstract interface. Components can easily be replaced by other components and it is generally easier to modify the structure of a system and to reuse components in other systems.

Components must interact during the simulation and this communication must be based on a defined protocol. LISA+ has the ability to define customized protocols that are tailored to the specific components and offer a clean interface. Ports of components can only be connected if they implement the same protocol.

More details on declaring, defining and using these protocols are given later. See Chapter 4 Protocols.

A port declaration has the format:

port_attributes port<protocol_name> instanceName[, instanceName2 …];

where:

port_attributes

can be a combination of the attributes master, slave, internal and addressable.

protocol_name

is the name of a protocol and can be considered to be a port type.

If a port has behavior that implements one or more protocol functions, the port declaration also has a body containing behavior declarations:

port_attributes port<protocol_name> instanceName
{
    behavior f {    }
    behavior g {    }
    // …
}
Copyright © 2007-2009 ARM Limited. All rights reserved.ARM DUI 0372G
Non-Confidential