2.6.1. Master, slave, and internal ports

Each port has a master and a slave side. Some ports of a component are typically exposed to the system outside of the component as master ports, for example a memory port of a CPU. Such ports have the master port attribute.

Some ports are intended to be exposed to the outside system as slave ports, for example an interrupt request port of a CPU. Such ports have the slave attribute.

Some ports are only used internally in a component, for example to receive callbacks from a subcomponent. Such ports neither expose their master side nor their slave side. Such ports have the internal attribute.

All ports must be either master or slave or internal.

A port cannot be master and slave at the same time, meaning it can not expose the master and the slave side at the same time to the outside world.

You can add the master or slave attribute to the internal keyword to indicate how the internal port is to be used, but this is not required.

Master ports always only implement the master behaviors of a protocol and slave ports always implement the slave behaviors of a protocol. Because most protocols only have slave behaviors, typically only the slave port has behaviors.


The implementation of protocol behaviors must be done inside the scope of the port declaration. All resources that have been declared within the component scope can be directly accessed.

Copyright © 2007-2009 ARM Limited. All rights reserved.ARM DUI 0372G