The connection section is used to connect component ports with each other.

The scope of the connection section is defined by the composition section. Only the component’s own ports and ports of components declared in the composition section can be connected in the connection section.

The connections section contains a list of connection statements. The syntax of a connection statement is shown in Example 2.25. MAR and SAR are the optional Master Address Range and Slave Address Range. The address range includes both the low address and high address.

masterComponent and slaveComponent can be the instance name of any subcomponent, as defined in the composition section, or the keyword self that stands for the component that contains the connection section. masterComponent is always the transaction initiator (master) and slaveComponent is the transaction receiver (slave).

masterComponent.masterPort[MAR] => slaveComponent.slavePort[SAR];

For addressable ports an address range must be specified. See Addressable ports. No address range can be specified, however, for non-addressable ports.

The following rules apply for address ranges:

Example 2.26 shows how ports are connected in the connection section.

component MyComponent
{
    composition
    {
        mem: MyMemory(size=0x1000);
        mem2: MyMemory(size=0x1000);
        otherComp: MyOtherComp;
        probe: MyProbe;
    }
    addressable master port<MyMemProtocol> memport;
    master port<MyOtherProtocol> otherPort;
    connection
    {
        // default bus slave comes first and gets all addresses which 
        // are not overridden by the other connection statements
        self.memport[0..0xffffffff] => probe.access;
        // addressable master ports can have address ranges
        self.memport[0..0xfff] => mem.access[0..0xfff];
        // this is equivalent to => mem2.access[0..0xfff]
        self.memport[0x1000..0x1fff] => mem2.access;

        self.otherPort => otherComp.otherPort;    
    }}

In Example 2.26, the port memport is an external port and probe is a component. The keyword self is used to identify that the external port memport is connected to the access port of the probe component.