6.10 Inline assembler Thumb instruction set restrictions in C and C++ code

The inline assembler supports Thumb state in ARM architectures v6T2, v6M, and v7. There are a number of Thumb-specific restrictions.

These restrictions are as follows:
  1. TBB, TBH, CBZ, and CBNZ instructions are not supported.
  2. In some cases, the compiler can replace IT blocks with branched code.
  3. The instruction width specifier .N denotes a preference, but not a requirement, to the compiler. This is because, in rare cases, optimizations and register allocation can make it inefficient to generate a 16-bit encoding.
For ARMv6 and lower architectures, the inline assembler does not assemble any Thumb instructions. Instead, on finding inline assembly while in Thumb state, the compiler switches to ARM state automatically. Code that relies on this switch is currently supported, but this practise is deprecated. For ARMv6T2 and higher, the automatic switch from Thumb to ARM state is made if the code is valid ARM assembly but not Thumb.
ARM state can be set deliberately. Inline assembly language can be included in a source file that contains code to be compiled for Thumb in ARMv6 and lower, by enclosing the functions containing inline assembly code between #pragma arm and #pragma thumb statements. For example:
...         // Thumb code
#pragma arm // ARM code. Switch code generation to the ARM instruction set so
            // that the inline assembler is available for Thumb in ARMv6 and lower.
int add(int i, int j)
{
    int res;
    __asm
    {
        ADD   res, i, j   // add here
    }
    return res;
}
#pragma thumb   // Thumb code. Switch back to the Thumb instruction set.
                // The inline assembler is no longer available for Thumb in ARMv6 and
                // lower.
The code must also be compiled using the --apcs /interwork compiler command-line option.
Related concepts
6.7 Restrictions on inline assembly operations in C and C++ code
6.8 Inline assembler register restrictions in C and C++ code
6.9 Inline assembler processor mode restrictions in C and C++ code
6.11 Inline assembler Vector Floating-Point (VFP) restrictions in C and C++ code
6.12 Inline assembler instruction restrictions in C and C++ code
6.13 Miscellaneous inline assembler restrictions in C and C++ code
Related reference
7.6 --apcs=qualifier...qualifier
9.71 Pragmas
Related information
Instruction width specifiers
IT
TBB and TBH
CBZ and CBNZ
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