ARM Compiler v5.04 for µVision armcc User Guide : 6.12 Inline assembler instruction restrictions in C and C++ code

6.12 Inline assembler instruction restrictions in C and C++ code

There are a number of instructions that the inline assembler does not support.

Specifically, the following instructions are not supported:

BKPT, BX, BXJ, and BLX instructions.

Note

You can insert a BKPT instruction in C and C++ code by using the __breakpoint() intrinsic.
LDR Rn, =expression pseudo-instruction. Use MOV Rn, expression instead. (This can generate a load from a literal pool.)
LDRT, LDRBT, STRT, and STRBT instructions.
MUL, MLA, UMULL, UMLAL, SMULL, and SMLAL flag setting instructions.
MOV or MVN flag-setting instructions where the second operand is a constant.
The special LDM instructions used in system or supervisor mode to load the user-mode banked registers, written with a ^ after the register list, such as:
```
LDMIA sp!, {r0-r12, lr, pc}^
```
ADR and ADRL pseudo-instructions.

Note

You can use MOV Rn, &expression;instead of the ADR and ADRL pseudo-instructions.
ARM recommends not using the LDREX and STREX instructions. This is because the compiler may generate loads and stores between LDREX and STREX, potentially clearing the exclusive monitor set by LDREX. This recommendation also applies to the byte, halfword, and doubleword variants LDREXB, STREXB, LDREXH, STREXH, LDREXD, and STREXD.