ARM Compiler v5.04 for µVision armcc User Guide : 6.17 Expansion of inline assembler instructions that use constants

6.17 Expansion of inline assembler instructions that use constants

A constant operand specified in an instruction is not limited to the values permitted by the instruction. Instead, the compiler might translate the instruction into a sequence of instructions with the same effect.

For example:

ADD r0,r0,#1023

might be translated into:

ADD r0,r0,#1024
SUB r0,r0,#1

Another example of expansion possibility is:

MOV rn,0x12345678

With the exception of coprocessor instructions, all ARM instructions with a constant operand support instruction expansion. In addition, the MUL instruction can be expanded into a sequence of adds and shifts when the third operand is a constant.

The effect of updating the CPSR by an expanded instruction is:

Arithmetic instructions set the NZCV flags correctly.
Logical instructions:
- Set the NZ flags correctly.
- Do not change the V flag.
- Corrupt the C flag.

Related concepts

6.16 Inline assembler and instruction expansion in C and C++ code

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