3.6 Compiler intrinsics for inserting optimization barriers

The optimization barrier intrinsics __schedule_barrier, __force_stores and __memory_changed let you override compiler optimizations by disabling instruction re-ordering and forcing memory updates.

The compiler can perform a range of optimizations, including re-ordering instructions and merging some operations. In some cases, such as system level programming where memory is being accessed concurrently by multiple processes, it might be necessary to disable instruction re-ordering and force memory to be updated.
The optimization barrier intrinsics __schedule_barrier, __force_stores and __memory_changed do not generate code, but they can result in slightly increased code size and additional memory accesses.

Note

On some systems the memory barrier intrinsics might not be sufficient to ensure memory consistency. For example, the __memory_changed intrinsic forces values held in registers to be written out to memory. However, if the destination for the data is held in a region that can be buffered it might wait in a write buffer. In this case you might also have to write to CP15 or use a memory barrier instruction to drain the write buffer. See the Technical Reference Manual for your ARM processor for more information.
Related reference
9.114 __force_stores intrinsic
9.118 __memory_changed intrinsic
9.130  __schedule_barrier intrinsic
Non-ConfidentialPDF file icon PDF versionARM DUI0375F
Copyright © 2007, 2008, 2011, 2012, 2014 ARM. All rights reserved.