4.44 Vector Floating-Point (VFP) architectures

ARM supports several versions of the VFP architecture, implemented in different ARM architectures.

VFP architectures provide both single and double precision operations. Many operations can take place in either scalar form or in vector form. Several versions of the architecture are supported, including:
  • VFPv2, implemented in:
    • VFP9-S, available as a separately licensable option for the ARM926E, ARM946E and ARM966E processors.
  • VFPv3, implemented on ARM architecture v7 and later. VFPv3 is backwards compatible with VFPv2, except that it cannot trap floating point exceptions. It requires no software support code. VFPv3 has 32 double-precision registers.
  • VFPv3_fp16, VFPv3 with half-precision extensions. These extensions provide conversion functions between half-precision floating-point numbers and single-precision floating-point numbers, in both directions. They can be implemented with any VFP implementation that supports single-precision floating-point numbers.
  • VFPv3-D16, an implementation of VFPv3 that provides 16 double-precision registers. It is implemented on ARM architecture v7 processors that support VFP without NEON technology.
  • VFPv3U, an implementation of VFPv3 that can trap floating-point exceptions. It requires software support code.
  • VFPv4, implemented on ARM architecture v7 and later. VFPv4 has 32 double-precision registers. VFPv4 adds both half-precision extensions and fused multiply-add instructions to the features of VFPv3.
  • VFPv4-D16, an implementation of VFPv4 that provides 16 double-precision registers. It is implemented on ARM architecture v7 processors that support VFP without NEON technology.
  • VFPv4U, an implementation of VFPv4 that can trap floating-point exceptions. It requires software support code.

Note

Particular implementations of the VFP architecture might provide additional implementation-specific functionality. For example, the VFP coprocessor hardware might include extra registers for describing exceptional conditions. This extra functionality is known as sub-architecture functionality.
Related concepts
4.41 Compiler support for floating-point arithmetic
4.42 Default selection of hardware or software floating-point support
4.43 Example of hardware and software support differences for floating-point arithmetic
4.45 Limitations on hardware handling of floating-point arithmetic
4.46 Implementation of Vector Floating-Point (VFP) support code
4.47 Compiler and library support for half-precision floating-point numbers
4.48 Half-precision floating-point number format
4.49 Compiler support for floating-point computations and linkage
4.50 Types of floating-point linkage
4.51 Compiler options for floating-point linkage and computations
Related reference
4.52 Floating-point linkage and computational requirements of compiler options
4.53 Processors and their implicit Floating-Point Units (FPUs)
Related information
ARM Application Note 133 - Using VFP with RVDS
Non-ConfidentialPDF file icon PDF versionARM DUI0375F
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