4.45 Limitations on hardware handling of floating-point arithmetic

ARM Vector Floating-Point (VFP) coprocessors are optimized to process well-defined floating-point code in hardware. Arithmetic operations that occur too rarely, or that are too complex, are not handled in hardware.

Instead, processing of these cases must be handled in software. This approach minimizes the amount of coprocessor hardware required and reduces costs.
Code provided to handle cases the VFP hardware is unable to process is known as VFP support code. When the VFP hardware is unable to deal with a situation directly, it bounces the case to VFP support code for more processing. For example, VFP support code might be called to process any of the following:
  • Floating-point operations involving NaNs.
  • Floating-point operations involving denormals.
  • Floating-point overflow.
  • Floating-point underflow.
  • Inexact results.
  • Division-by-zero errors.
  • Invalid operations.
When support code is in place, the VFP supports a fully IEEE 754-compliant floating-point model.
Related concepts
4.41 Compiler support for floating-point arithmetic
4.42 Default selection of hardware or software floating-point support
4.43 Example of hardware and software support differences for floating-point arithmetic
4.44 Vector Floating-Point (VFP) architectures
4.46 Implementation of Vector Floating-Point (VFP) support code
4.47 Compiler and library support for half-precision floating-point numbers
4.48 Half-precision floating-point number format
4.49 Compiler support for floating-point computations and linkage
4.50 Types of floating-point linkage
4.51 Compiler options for floating-point linkage and computations
Related reference
4.52 Floating-point linkage and computational requirements of compiler options
4.53 Processors and their implicit Floating-Point Units (FPUs)
Related information
Institute of Electrical and Electronics Engineers
Non-ConfidentialPDF file icon PDF versionARM DUI0375F
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