ARM® Compiler toolchain v5.02 for µVision Using the Assembler

List of Topics

Conventions and feedback
Overview of the Assembler
About the ARM Compiler toolchain assemblers
Key features of the assembler
How the assembler works
Directives that can be omitted in pass 2 of the assembler
Overview of the ARM Architecture
About the ARM architecture
ARM, Thumb, and ThumbEE instruction sets
Changing between ARM, Thumb, and ThumbEE state
Processor modes, and privileged and unprivileged software execution
Processor modes in ARMv6-M and ARMv7-M
VFP coprocessor
ARM registers
General-purpose registers
Register accesses
Predeclared core register names
Predeclared extension register names
Predeclared coprocessor names
Program Counter
Application Program Status Register
The Q flag
Current Program Status Register
Saved Program Status Registers (SPSRs)
Instruction set overview
Media processing instructions
Access to the inline barrel shifter
Structure of Assembly Language Modules
Syntax of source lines in assembly language
ELF sections and the AREA directive
An example ARM assembly language module
Writing ARM Assembly Language
Unified Assembler Language
Subroutines calls
Load immediates into registers
Load immediate values using MOV and MVN
Load 32-bit values to a register using MOV32
Load immediate 32-bit values to a register using LDR Rd, =const
Literal pools
Load addresses into registers
Load addresses to a register using ADR
Load addresses to a register using ADRL
Load addresses to a register using LDR Rd, =label
Other ways to load and store registers
Load and store multiple register instructions
Load and store multiple instructions available in ARM and Thumb
Stack implementation using LDM and STM
Stack operations for nested subroutines
Block copy with LDM and STM
Memory accesses
Read-Modify-Write procedure
Optional hash
Use of macros
Test-and-branch macro example
Unsigned integer division macro example
Instruction and directive relocations
Symbol versions
Frame directives
Exception tables and Unwind tables
Assembly language changes after RVCTv2.1
Condition Codes
Conditional instructions
Conditional execution in ARM state
Conditional execution in Thumb state
Updates to the ALU status flags
Condition code suffixes
Condition code meanings
Benefits of using conditional execution
Illustration of the benefits of using conditional instructions
Optimization for execution speed
Using the Assembler
Assembler command line syntax
Assembler commands listed in groups
Specify command line options with an environment variable
Using stdin to input source code to the assembler
Built-in variables and constants
Versions of armasm
Diagnostic messages
Interlocks diagnostics
IT block generation
Thumb branch target alignment
Thumb code size diagnostics
ARM and Thumb instruction portability diagnostics
Instruction width
2 pass assembler diagnostics
Conditional assembly
Using the C preprocessor
Address alignment
Instruction width selection in Thumb
Symbols, Literals, Expressions, and Operators
Symbol naming rules
Numeric constants
Assembly time substitution of variables
Register-relative and PC-relative expressions
Labels for PC-relative addresses
Labels for register-relative addresses
Labels for absolute addresses
Local labels
Syntax of local labels
String expressions
String literals
Numeric expressions
Numeric literals
Floating-point literals
Logical expressions
Logical literals
Unary operators
Binary operators
Multiplicative operators
String manipulation operators
Shift operators
Addition, subtraction, and logical operators
Relational operators
Boolean operators
Operator precedence
Difference between operator precedence in armasm and C
VFP Programming
Architecture support for VFP
Half-precision extension
Fused Multiply-Add extension
Extension register bank mapping
VFP views of the extension register bank
Load values to VFP registers
Conditional execution of VFP instructions
Floating-point exceptions
VFP data types
Extended notation
VFP system registers
FPSCR, the floating-point status and control register
FPEXC, the floating-point exception register
FPSID, the floating-point system ID register
Flush-to-zero mode
When to use flush-to-zero mode
The effects of using flush-to-zero mode
Operations not affected by flush-to-zero mode
VFP vector mode
Vectors in the VFP extension register bank
VFP vector wrap-around
VFP vector stride
Restriction on vector length
Control of scalar, vector, and mixed operations
VFP directives and vector notation
Pre-UAL VFP mnemonics
Vector notation

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Revision History
Revision AMay 2007Release for RVCT v3.1 for µVision
Revision BDecember 2008Release for RVCT v4.0 for µVision
Revision CJune 2011Release for ARM Compiler toolchain v4.1 for µVision
Revision DJuly 2012Release for ARM Compiler toolchain v5.02 for µVision
Copyright © 2007-2008, 2011-2012 ARM. All rights reserved.ARM DUI 0379D