In ARMv7-R, the A bit in the System Control Register, SCTLR,
controls whether alignment checking is enabled or disabled. In ARMv7-M, the
UNALIGN_TRP bit, bit 3, in the Configuration and Control
Register (CCR) controls this.
If alignment checking is enabled, all unaligned word and halfword transfers cause an
alignment exception. If disabled, unaligned accesses are permitted for the
TBH instructions. Other data-accessing instructions always cause an
alignment exception for unaligned data.
LDRD, the specified address must be
ARMv5 and earlier
For word transfers, you must ensure that addresses are 4-byte aligned.
Otherwise, if alignment checking is enabled, an alignment exception occurs. If alignment
checking is unavailable, or if it is available but disabled, the following occur:
LDM, the specified address is rounded down
to a multiple of four.
Four bytes of data are loaded from the resulting address.
The loaded data is rotated right by one, two or three bytes
according to bits [1:0] of the address.
For a little-endian memory system, this causes the addressed byte to
occupy the least significant byte of the register. For a big-endian memory system, it
causes the addressed byte to occupy:
Addresses must be halfword-aligned for halfword transfers, and doubleword-aligned for