## 8.21 Control of scalar, vector, and mixed operations

Whether a VFP arithmetic instruction operates on scalars, vectors, or a mixture of both depends on the LEN bits in the FPSCR and also on which register bank the destination and operand registers are in.

Use the `LEN` bits in the `FPSCR` to control the length of vectors. When `LEN` is 1 all VFP operations are scalar.
When `LEN` is greater than 1, the VFP operation can be scalar, vector or mixed. The behavior of VFP arithmetic operations depends on which register bank the destination and operand registers are in.
The first bank of registers, s0 to s7 or d0 to d3 and the fifth bank of registers d16 to d19 are scalar banks. All other banks are vector banks. A vector operation or mixed operation is one where the destination register is in one of the vector banks.
Given instructions of the following general forms:
```    `Op`  `Fd`,`Fn`,`Fm`
`Op`  `Fd`,`Fm````
where:
`Op`
is the VFP instruction.
`Fd`
is the destination register.
`Fn`
is an operand register.
`Fm`
is the only or second operand register.
the behavior of the operation is as follows:
• If `Fd` is in the first or fifth bank of registers then the operation is scalar.
• If `Fm` is in the first or fifth bank of registers, but `Fd` is not, then the operation is mixed.
• If neither `Fd` nor `Fm` are in the first or fifth bank of registers, the operation is vector.
In scalar operations, `Op` acts on the value in `Fm`, and the value in `Fn` if present. The result is placed in `Fd`.
In vector operations, `Op` acts on the values in the vector starting at `Fm`, together with the values in the vector starting at `Fn` if present. The results are placed in the vector starting at `Fd`.
In mixed operations, with a single operand, `Op` acts on the single value in `Fm` and `LEN` copies of the result are placed in the vector starting at `Fd`.
In mixed operations, with two operands, `Op` acts on the single value in `Fm`, together with the values in the vector starting at `Fn`. The results are placed in the vector starting at `Fd`.
##### Related concepts
8.17 Vectors in the VFP extension register bank
8.18 VFP vector wrap-around
8.19 VFP vector stride
8.20 Restriction on vector length
##### Related information
ARM Architecture Reference Manual
 Non-Confidential PDF version ARM DUI0379G Copyright © 2007, 2008, 2011, 2012, 2014, 2015 ARM. All rights reserved.