10.17 BFC

Bit Field Clear.


BFC{cond} Rd, #lsb, #width
is an optional condition code.
is the destination register.
is the least significant bit that is to be cleared.
is the number of bits to be cleared. width must not be 0, and (width+lsb) must be less than or equal to 32.


Clears adjacent bits in a register. width bits in Rd are cleared, starting at lsb. Other bits in Rd are unchanged.

Register restrictions

You cannot use PC for any register.
You can use SP in the BFC ARM instruction but this is deprecated in ARMv6T2 and above. You cannot use SP in the BFC Thumb instruction.

Condition flags

The BFC instruction does not change the flags.


This ARM instruction is available in ARMv6T2 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above.
There is no 16-bit version of this instruction in Thumb.
Related reference
10.8 Condition code suffixes
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