10.58 MRC and MRC2

Move to ARM Register from Coprocessor. Depending on the coprocessor, you might be able to specify various additional operations.


MRC{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
MRC2{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
is an optional condition code. In ARM code, cond is not permitted for MRC2.
is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.
is a 3-bit coprocessor-specific opcode.
is an optional 3-bit coprocessor-specific opcode.
is the ARM destination register. Rt must not be PC.
Rt can be APSR_nzcv. This means that the coprocessor executes an instruction that changes the value of the condition flags in the APSR.
CRn, CRm
are coprocessor registers.


The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.


The MRC ARM instruction is available in all versions of the ARM architecture.
The MRC2 ARM instruction is available in ARMv5T and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There are no 16-bit versions of these instructions in Thumb.
Related reference
10.8 Condition code suffixes
Non-ConfidentialPDF file icon PDF versionARM DUI0379G
Copyright © 2007, 2008, 2011, 2012, 2014, 2015 ARM. All rights reserved.