10.89 ROR

Rotate Right. This instruction is a preferred synonym for MOV instructions with shifted register operands.


ROR{S}{cond} Rd, Rm, Rs
ROR{S}{cond} Rd, Rm, #sh
is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
is the destination register.
is the register holding the first operand. This operand is shifted right.
is a register holding a shift value to apply to the value in Rm. Only the least significant byte is used.
is a constant shift. The range of values is 1-31.


ROR provides the value of the contents of a register rotated by a value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.

Restrictions in Thumb code

Thumb instructions must not use PC or SP.

Use of SP and PC in ARM instructions

You can use SP in these ARM instructions but this is deprecated in ARMv6T2 and above.
You cannot use PC in instructions with the ROR{S}{cond} Rd, Rm, Rs syntax. You can use PC for Rd and Rm in the other syntax, but this is deprecated in ARMv6T2 and above.
If you use PC as Rm, the value used is the address of the instruction plus 8.
If you use PC as Rd:
  • Execution branches to the address corresponding to the result.
  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions.


    The ARM instruction RORS{cond} pc,Rm,#sh always disassembles to the preferred form MOVS{cond} pc,Rm{,shift}.


Do not use the S suffix when using PC as Rd in User mode or System mode. The assembler cannot warn you about this because it has no information about what the processor mode is likely to be at execution time.
You cannot use PC for Rd or any operand in this instruction if it has a register-controlled shift.

Condition flags

If S is specified, the instruction updates the N and Z flags according to the result.
The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

16-bit instructions

The following forms of this instruction are available in Thumb code, and are 16-bit instructions:
RORS Rd, Rd, Rs
Rd and Rs must both be Lo registers. This form can only be used outside an IT block.
ROR{cond} Rd, Rd, Rs
Rd and Rs must both be Lo registers. This form can only be used inside an IT block.


This ARM instruction is available in all architectures.
This 32-bit Thumb instruction is available in ARMv6T2 and above.
This 16-bit Thumb instruction is available in ARMv4T and above.


    ROR     r4, r5, r6
Related reference
10.55 MOV
10.8 Condition code suffixes
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