10.96 SBC

Subtract with Carry.


SBC{S}{cond} {Rd}, Rn, Operand2
is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
is an optional condition code.
is the destination register.
is the register holding the first operand.
is a flexible second operand.


The SBC (Subtract with Carry) instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one.
You can use SBC to synthesize multiword arithmetic.
In certain circumstances, the assembler can substitute one instruction for another. Be aware of this when reading disassembly listings.

Use of PC and SP in Thumb instructions

You cannot use PC (R15) for Rd, or any operand.
You cannot use SP (R13) for Rd, or any operand.

Use of PC and SP in ARM instructions

You cannot use PC for Rd or any operand in an SBC instruction that has a register-controlled shift.
Use of PC for any operand in instructions without register-controlled shift, is deprecated.
If you use PC (R15) as Rn or Rm, the value used is the address of the instruction plus 8.
If you use PC as Rd:
  • Execution branches to the address corresponding to the result.
  • If you use the S suffix, see the SUBS pc,lr instruction.
Use of SP in SBC ARM instructions is deprecated.


The deprecation of SP and PC in ARM instructions is only in ARMv6T2 and above.

Condition flags

If S is specified, the SBC instruction updates the N, Z, C and V flags according to the result.

16-bit instructions

The following forms of this instruction are available in Thumb code, and are 16-bit instructions:
SBCS Rd, Rd, Rm
Rd and Rm must both be Lo registers. This form can only be used outside an IT block.
SBC{cond} Rd, Rd, Rm
Rd and Rm must both be Lo registers. This form can only be used inside an IT block.

Multiword arithmetic examples

These instructions subtract one 96-bit integer contained in R9, R10, and R11 from another 96-bit integer contained in R6, R7, and R8, and place the result in R3, R4, and R5:
    SUBS    r3, r6, r9
    SBCS    r4, r7, r10
    SBC     r5, r8, r11
For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid:
    SUBS    r6, r6, r9
    SBCS    r9, r2, r1
    SBC     r2, r8, r11
Related reference
10.3 Flexible second operand (Operand2)
10.8 Condition code suffixes
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