10.115 SMLSD

Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation.

Syntax

SMLSD{X}{cond} Rd, Rn, Rm, Ra
where:
cond
is an optional condition code.
X
is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
Rd
is the destination register.
Rn, Rm
are the registers holding the operands.
Ra
is the register holding the accumulate operand.

Operation

SMLSD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then subtracts the second product from the first, adds the difference to the value in Ra, and stores the result to Rd.

Register restrictions

You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

This instruction does not change the flags.

Architectures

This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, this instruction is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.

Examples

    SMLSD       r1, r2, r0, r7
    SMLSDX      r11, r10, r2, r3
Related reference
10.8 Condition code suffixes
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