10.121 SMULxy

Signed Multiply, with 16-bit operands and a 32-bit result.


SMUL<x><y>{cond} {Rd}, Rn, Rm
is either B or T. B means use the bottom half (bits [15:0]) of Rn, T means use the top half (bits [31:16]) of Rn.
is either B or T. B means use the bottom half (bits [15:0]) of Rm, T means use the top half (bits [31:16]) of Rm.
is an optional condition code.
is the destination register.
Rn, Rm
are the registers holding the values to be multiplied.


SMULxy multiplies the 16-bit signed integers from the selected halves of Rn and Rm, and places the 32-bit result in Rd.

Register restrictions

You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

These instructions do not affect the N, Z, C, or V flags.


This ARM instruction is available in ARMv6 and above, and E variants of ARMv5T.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.


    SMULTBEQ    r8, r7, r9
Related reference
10.60 MRS (PSR to general-purpose register)
10.63 MSR (general-purpose register to PSR)
10.8 Condition code suffixes
Non-ConfidentialPDF file icon PDF versionARM DUI0379G
Copyright © 2007, 2008, 2011, 2012, 2014, 2015 ARM. All rights reserved.