10.124 SMUSD

Dual 16-bit Signed Multiply with Subtraction of products, and optional exchange of operand halves.

Syntax

SMUSD{X}{cond} {Rd}, Rn, Rm
where:
X
is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
cond
is an optional condition code.
Rd
is the destination register.
Rn, Rm
are the registers holding the operands.

Operation

SMUSD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then subtracts the second product from the first, and stores the difference to Rd.

Register restrictions

You cannot use PC for any register.
You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Architectures

This ARM instruction is available in ARMv6 and above.
This 32-bit Thumb instruction is available in ARMv6T2 and above. For the ARMv7-M architecture, it is only available in an ARMv7E-M implementation.
There is no 16-bit version of this instruction in Thumb.

Example

    SMUSDXNE    r0, r1, r2
Related reference
10.8 Condition code suffixes
Non-ConfidentialPDF file icon PDF versionARM DUI0379G
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