Operation
The SVC
instruction causes an exception.
This means that the processor mode changes to Supervisor, the CPSR
is saved to the Supervisor mode SPSR, and execution branches to
the SVC vector.
imm
is ignored by the
processor. However, it can be retrieved by the exception handler
to determine what service is being requested.
Note
SVC
was called SWI
in
earlier versions of the ARM assembly language. SWI
instructions disassemble
to SVC
, with a comment to say that this
was formerly SWI
.
Architectures
This ARM instruction is available in all versions of the ARM
architecture.
This 16-bit Thumb instruction is available in all T variants
of the ARM architecture.
There is no 32-bit version of this instruction in Thumb.