Fused floatingpoint multiply accumulate and fused floatingpoint multiply subtract, with optional negation.
Syntax
VF
{N
}op
{cond
}.F64
{Dd
}, Dn
, Dm
VF
{N
}op
{cond
}.F32
{Sd
}, Sn
, Sm
where:
op
is one of MA
or MS
.
N

negates the final result.
cond
is an optional condition code.
Sd
, Sn
, Sm
are the singleprecision registers for the result
and operands.
Dd
, Dn
, Dm
are the doubleprecision registers for the result
and operands.
Operation
VFMA
multiplies the values in the operand
registers, adds the value in the destination register, and places the final result in the
destination register. The result of the multiply is not rounded before the accumulation.
VFMS
multiplies the values in the operand
registers, subtracts the product from the value in the destination register, and places the
final result in the destination register. The result of the multiply is not rounded before
the subtraction.
In each case, the final result is negated if the N
option is used.
Floatingpoint exceptions
These instructions can produce Input Denormal, Invalid Operation,
Overflow, Underflow, or Inexact exceptions.