11.16 VMLS (floating-point)

Floating-point multiply subtract.

Syntax

VMLS{cond}.F32 Sd, Sn, Sm
VMLS{cond}.F64 Dd, Dn, Dm
where:
cond
is an optional condition code.
Sd, Sn, Sm
are the single-precision registers for the result and operands.
Dd, Dn, Dm
are the double-precision registers for the result and operands.

Operation

The VMLS instruction multiplies the values in the operand registers, subtracts the result from the value in the destination register, and places the final result in the destination register.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow, Underflow, Inexact, or Input Denormal exceptions.
Related reference
10.8 Condition code suffixes
Non-ConfidentialPDF file icon PDF versionARM DUI0379G
Copyright © 2007, 2008, 2011, 2012, 2014, 2015 ARM. All rights reserved.