11.24 VNEG (floating-point)

Floating-point negate.


VNEG{cond}.F32 Sd, Sm
VNEG{cond}.F64 Dd, Dm
is an optional condition code.
Sd, Sm
are the single-precision registers for the result and operand.
Dd, Dm
are the double-precision registers for the result and operand.


The VNEG instruction takes the contents of Sm or Dm, changes the sign bit, and places the result in Sd or Dd. This gives the negation of the value.
If the operand is a NaN, the sign bit is changed, but no exception is produced.

Floating-point exceptions

VNEG instructions do not produce any exceptions.
Related reference
10.8 Condition code suffixes
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