11.27 VNMUL (floating-point)

Floating-point multiply with negation.


VNMUL{cond}.F32 {Sd,} Sn, Sm
VNMUL{cond}.F64 {Dd,} Dn, Dm
is an optional condition code.
Sd, Sn, Sm
are the single-precision registers for the result and operands.
Dd, Dn, Dm
are the double-precision registers for the result and operands.


The VNMUL instruction multiplies the values in the operand registers and places the negated result in the destination register.

Floating-point exceptions

This instruction can produce Invalid Operation, Overflow, Underflow, Inexact, or Input Denormal exceptions.
Related reference
10.8 Condition code suffixes
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