The following figure shows the views of the VFP extension register bank,
and the overlap between the different size registers. For example, the 64-bit register
D0 is an alias for two consecutive 32-bit registers
Figure 8-1 VFP extension register bank
The figure applies to a VFP implementation with 32 double precision
registers. The following versions of VFP use 16 double precision registers,
The aliased views enable half-precision,
single-precision, and double-precision values to coexist in different non-overlapped
registers at the same time.
You can also use the same overlapped registers to store
half-precision, single-precision, and double-precision values at different times.
Do not attempt to use overlapped 32-bit and 64-bit
registers at the same time because it creates meaningless results.
The mapping between the registers is as follows:
For example, you can access the least significant half
of the elements of a vector in
D6 by referring to
S12, and the most significant half of the elements by referring