11.33 VSTR (post-increment and pre-decrement, floating-point)

Pseudo-instruction that stores extension registers with post-increment and pre-decrement forms.

Note

There are also VLDR and VSTR instructions without post-increment and pre-decrement.

Syntax

VSTR{cond}{.size} Fd, [Rn], #offset ; post-increment
VSTR{cond}{.size} Fd, [Rn, #-offset]! ; pre-decrement
where:
cond
is an optional condition code.
size
is an optional data size specifier. Must be 32 if Fd is an S register, or 64 if Fd is a D register.
Fd
is the extension register to be saved. It can be either a double precision (Dd) or a single precision (Sd) register.
Rn
is the ARM register holding the base address for the transfer.
offset
is a numeric expression that must evaluate to a numeric value at assembly time. The value must be 4 if Fd is an S register, or 8 if Fd is a D register.

Operation

The post-increment instruction increments the base address in the register by the offset value, after the transfer. The pre-decrement instruction decrements the base address in the register by the offset value, and then performs the transfer using the new address in the register. This pseudo-instruction assembles to a VSTM instruction.
Related reference
11.32 VSTR (floating-point)
11.31 VSTM (floating-point)
10.8 Condition code suffixes
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