Cortex-M1 FPGA Development Kit Cortex-M1 User Guide: 5.2.2. Interrupt Clear-Enable Register

Use the Interrupt Clear-Enable Register to:

Each bit in the register corresponds to one of 32 interrupts. Setting an Interrupt Clear-Enable Register bit disables the corresponding interrupt.

Writing 1 to an Interrupt Clear-Enable Register bit does not affect currently active interrupts. It only prevents new activations.

The register address, access type, and reset value are:

Figure 5.2 shows the bit assignments of the Interrupt Clear-Enable Register.

Figure 5.2. Interrupt Clear-Enable Register bit assignments

Table 5.3 lists the bit assignments of the Interrupt Clear-Enable Register.

Table 5.3. Interrupt Clear-Enable Register bit assignments

Bits	Field	Function
[31:0]	CLRENA	Interrupt clear-enable bits. For writes: 1 = disable interrupt 0 = no effect. For reads: 1 = interrupt enabled 0 = interrupt disabled. Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state. Reset clears the CLRENA field.

Bits

Field

Function

[31:0]

CLRENA

Interrupt clear-enable bits.

For writes:

1 = disable interrupt

0 = no effect.

For reads:

1 = interrupt enabled

0 = interrupt disabled.

Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state.

Reset clears the CLRENA field.

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