Cortex™-M1 FPGA Development Kit Cortex-M1 User Guide

Altera Edition version 1.1


Table of Contents

Preface
About this guide
Intended audience
Using this guide
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the processor
1.2. Functional overview
1.2.1. Cortex-M1 Core
1.2.2. TCMs
2. Programmer's Model
2.1. About the programmer’s model
2.2. Modes of operation and execution
2.3. Registers
2.3.1. General purpose registers
2.3.2. Stacks
2.3.3. Link Register
2.3.4. Program Counter
2.4. Program status register
2.4.1. Application Processor Status Register
2.4.2. Interrupt Processor Status Register
2.4.3. Execution Processor Status Register
2.4.4. Special-Purpose Priority Mask Register
2.4.5. Special-Purpose Control Register
2.5. Data types
2.6. Exceptions
2.6.1. Exception types
2.6.2. Exception priority
2.6.3. Exception entry
2.6.4. Exception exit
2.7. LOCKUP
2.8. Memory model
2.8.1. Processor memory map
2.8.2. Memory types and memory transactions
3. Processor Instantiation and Configuration
3.1. About processor instantiation and configuration
3.2. Processor instantiation
3.3. Processor configuration
3.4. Configuration considerations
3.5. System connectivity
3.5.1. Avalon interfaces
3.5.2. Exported signals
3.5.3. Resets and clocks
3.6. Simulation considerations
4. System Timer
4.1. About the system timer
4.2. System timer registers
4.2.1. SysTick Control and Status Register
4.2.2. SysTick Reload Value Register
4.2.3. SysTick Current Value Register
4.2.4. SysTick Calibration Value Register
5. Nested Vectored Interrupt Controller
5.1. About the NVIC
5.2. NVIC register descriptions
5.2.1. Interrupt Set-Enable Register
5.2.2. Interrupt Clear-Enable Register
5.2.3. Interrupt Set-Pending Register
5.2.4. Interrupt Clear-Pending Register
5.2.5. Interrupt Priority Registers
5.3. Level versus pulse interrupts
5.4. Resampling level interrupts
6. System Control Block
6.1. About the system control block
6.2. System control block registers
6.2.1. CPUID Base Register
6.2.2. Interrupt Control State Register
6.2.3. Application Interrupt and Reset Control Register
6.2.4. Configuration and Control Register
6.2.5. System handler priority registers
6.2.6. System Handler Control and State Register
A. Embedded Software Examples
A.1. About embedded software examples
A.2. C declarations
A.3. Using memory barrier instructions for memory transactions
A.4. Examples of using the system timer
A.5. Example of how to configure and enable an external interrupt
A.6. Example of how to configure and schedule a PendSV exception
Glossary

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Product Status

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Revision History
Revision A21 November 2007First release for version 1.0
Revision B22 August 2008First release for version 1.1
Copyright © 2007, 2008 ARM Limited. All rights reserved.ARM DUI 0395B
Non-Confidential